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GET /api/1.1/patches/2229463/?format=api
{ "id": 2229463, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229463/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428093339.2087081-4-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428093339.2087081-4-peter.maydell@linaro.org>", "date": "2026-04-28T09:33:38", "name": "[3/4] hw/xtensa/mx_pic: Specify xtensa_mx_pic_ops .impl settings", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "264f099d5ae2ad6a88868060e16d876049bba6aa", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428093339.2087081-4-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501806, "url": "http://patchwork.ozlabs.org/api/1.1/series/501806/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501806", "date": "2026-04-28T09:33:37", "name": "MemoryRegionOps .impl cleanups", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501806/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229463/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229463/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nT+It1a1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4ZzK2hSvz1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 28 Apr 2026 19:35:09 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHepD-0003RL-E9; Tue, 28 Apr 2026 05:33:51 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHepA-0003OF-KX\n for qemu-devel@nongnu.org; Tue, 28 Apr 2026 05:33:48 -0400", "from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHep8-0007RH-UJ\n for qemu-devel@nongnu.org; Tue, 28 Apr 2026 05:33:48 -0400", "by mail-wm1-x32e.google.com with SMTP id\n 5b1f17b1804b1-4891cd41959so94716485e9.3\n for <qemu-devel@nongnu.org>; Tue, 28 Apr 2026 02:33:46 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The xtensa mx-pic interrupt controller has a rather odd register\nsetup, where some registers are 32 bits but are decoded at offsets\nonly one apart from each other. The QEMU implementation handles this\ncorrectly, but it did not set .impl.unaligned = true. This has\nworked up til now because QEMU has entirely ignored .impl.unaligned,\nand just allowed through unaligned accesses when\n.valid.unaligned is set.\n\nTo allow the possibility of properly implementing synthesis of\nunaligned accesses by the memory subsystem when they are valid but\nthe device doesn't implement them, and for clarity of intention,\nstate explicitly that this MR's read and write functions directly\nhandle unaligned accesses, by setting .impl.unaligned = true.\n\nWhile we are adjusting the MemoryRegionOps, we set also the minimum\nand maximum allowed access sizes. Since the only way to get at this\ndevice is via the CPU's RER and WER instructions, which always\noperate at 32-bit sizes (see the HELPER(rer) and HELPER(wer)\nfunctions in target/xtensa/op_helper.c), we know we will always get\n32-bit accesses. Specify explicitly that that is what is valid and\nimplemented for the MR.\n\nAdd a comment to clarify that the hardware behaviour here is not\n\"true memory-mapped registers\", so the odd-looking implementation is\ncorrect.\n\nBased-on-a-patch-by: CJ Chen <cjchen@igel.co.jp>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/xtensa/mx_pic.c | 27 +++++++++++++++++++++++++++\n 1 file changed, 27 insertions(+)", "diff": "diff --git a/hw/xtensa/mx_pic.c b/hw/xtensa/mx_pic.c\nindex 07c3731aef..098c1aaf85 100644\n--- a/hw/xtensa/mx_pic.c\n+++ b/hw/xtensa/mx_pic.c\n@@ -69,6 +69,26 @@ struct XtensaMxPic {\n } cpu[MX_MAX_CPU];\n };\n \n+/*\n+ * Note that decode for these registers is rather strange by the usual\n+ * MMIO standards -- the MIROUT and MIPICAUSE areas can be read and\n+ * written at 32-bit length, returning different values for each byte\n+ * offset, because the low bits of the address are treated as selecting\n+ * an IRQ or a processor:\n+ *\n+ * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p\n+ * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p\n+ *\n+ * This is because (like x86 IO port in/out accesses) the offset is\n+ * not a memory-mapped address but is really a register number,\n+ * accessed via the Xtensa RER/WER \"external register\" instructions.\n+ *\n+ * We set .valid and .impl to both allow unaligned = true to permit\n+ * these byte-offsets. Because this device is not a true memory mapped\n+ * device but is accessible only via the Xtensa RER/WER \"external\n+ * register\" interface, all accesses are guaranteed 32 bits.\n+ */\n+\n static uint64_t xtensa_mx_pic_ext_reg_read(void *opaque, hwaddr offset,\n unsigned size)\n {\n@@ -267,7 +287,14 @@ static const MemoryRegionOps xtensa_mx_pic_ops = {\n .read = xtensa_mx_pic_ext_reg_read,\n .write = xtensa_mx_pic_ext_reg_write,\n .endianness = DEVICE_NATIVE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ .unaligned = true,\n+ },\n .valid = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n .unaligned = true,\n },\n };\n", "prefixes": [ "3/4" ] }