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GET /api/1.1/patches/2229438/?format=api
{ "id": 2229438, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229438/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428-t_power_on_fux-v5-2-f1ef926a91ff@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428-t_power_on_fux-v5-2-f1ef926a91ff@oss.qualcomm.com>", "date": "2026-04-28T08:37:16", "name": "[v5,2/3] PCI: dwc: Add helper to Program T_POWER_ON", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4e370da51d5f8d4bf4ad6d07242906f5944104f7", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.1/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428-t_power_on_fux-v5-2-f1ef926a91ff@oss.qualcomm.com/mbox/", "series": [ { "id": 501799, "url": "http://patchwork.ozlabs.org/api/1.1/series/501799/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501799", "date": "2026-04-28T08:37:15", "name": "PCI: qcom: Program T_POWER_ON value for L1.2 exit timing", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501799/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229438/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229438/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53314-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ju8d2tQv;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Un0j7zxs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20260428-t_power_on_fux-v5-2-f1ef926a91ff@oss.qualcomm.com>", "References": "<20260428-t_power_on_fux-v5-0-f1ef926a91ff@oss.qualcomm.com>", "In-Reply-To": "<20260428-t_power_on_fux-v5-0-f1ef926a91ff@oss.qualcomm.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>", "Cc": "linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com,\n quic_vbadigan@quicinc.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,\n Shawn Lin <shawn.lin@rock-chips.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777365442; l=2919;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=uCwOE5ysFbUangZmfLBwMHPVZzeHW0tDINBDTiiyaU0=;\n b=JVjkJji61wI6a1eKinXgcH5AhzCDvNTpDoi/tKNk+aFklOUPuhvM+KsJ0w9o+z9PoxvXVRVld\n TJDxuns7HoND922F6EAZ+NI0u3YN2JJvp8Ue/k9HgI7yDUUXKCadR6/", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Authority-Analysis": "v=2.4 cv=Zs3d7d7G c=1 sm=1 tr=0 ts=69f071d0 cx=c_pps\n a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22\n a=s8YR1HE3AAAA:8 a=EUspDBNiAAAA:8 a=kXhGf0cxdCgfIYue-YsA:9 a=3ZKOabzyN94A:10\n a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=jGH_LyMDp9YhSvY-UuyI:22", "X-Proofpoint-ORIG-GUID": "ocPlGxh_SMqfJlUbWFencxRfEKtwPPZD", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI4MDA3OSBTYWx0ZWRfXzCPbKK2JYkXq\n z/FSs0Z3d9JOiZuHMaHXI6AQ1NckYmd1AcGmjyeCDngszOav6nHZYgljiCONf2s82bipQdEnlCE\n kRv8+c4qmjJ9NBqM/9gEVe6ChHfX0V+2GPU5/zgWjSkvdZogDLZjpPUFhonuU3GCMvlH1yBVMop\n bBVTk+9efDitFJiP8dGBJKyPb7Kl0fGg1R1NbQLrOxLQUP+NGxLa+Z1i4b81YNh9EL5KsrFp3EJ\n gf/iMBGmNrzON0sms3pWsR6yB+Hkpta9Wv4DGgkN8rX6L8wbihSRvXK3VI68CLZtZQO/OmSXs5f\n nniiVxm/b7D2PZb3uDUNDGbJkryrt6f7oTxXLWdtsty589C2qpsQwrv+98x/sG58pwjXEnAzILB\n Ql40ug5eXfNJlckOooOYgnr5ukFn/vm4LKE1C3S/hZeucOOwhYllZcryvMaW5SDPux/KZhXBUkC\n aEjci30v2gwl5qhWctA==", "X-Proofpoint-GUID": "ocPlGxh_SMqfJlUbWFencxRfEKtwPPZD", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_02,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 lowpriorityscore=0 phishscore=0 bulkscore=0 malwarescore=0\n impostorscore=0 adultscore=0 suspectscore=0 spamscore=0 clxscore=1015\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280079" }, "content": "The T_POWER_ON indicates the time (in μs) that a Port requires the port\non the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ#\nasserted before actively driving the interface. This value is used by\nthe ASPM driver to compute the LTR_L1.2_THRESHOLD.\n\nCurrently, some controllers exposes T_POWER_ON value of zero in the L1SS\ncapability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations,\nwhich can result in improper L1.2 exit behavior and if AER happens to be\nsupported and enabled, the error may be *reported* via AER.\n\nAdd a helper to override T_POWER_ON value by the DWC controller drivers.\n\nTested-by: Shawn Lin <shawn.lin@rock-chips.com>\nReviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-designware.c | 28 ++++++++++++++++++++++++++++\n drivers/pci/controller/dwc/pcie-designware.h | 1 +\n 2 files changed, 29 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex c11cf61b8319..9e5fc9935a4e 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -1249,6 +1249,34 @@ void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci)\n \tdw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap);\n }\n \n+/* TODO: Need to handle multi Root Ports */\n+void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on)\n+{\n+\tu8 scale, value;\n+\tu16 offset;\n+\tu32 val;\n+\n+\tif (!t_power_on)\n+\t\treturn;\n+\n+\toffset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);\n+\tif (!offset)\n+\t\treturn;\n+\n+\tpcie_encode_t_power_on(t_power_on, &scale, &value);\n+\n+\tdw_pcie_dbi_ro_wr_en(pci);\n+\n+\tval = dw_pcie_readl_dbi(pci, offset + PCI_L1SS_CAP);\n+\tval &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE);\n+\tFIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, &val, scale);\n+\tFIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, value);\n+\n+\tdw_pcie_writel_dbi(pci, offset + PCI_L1SS_CAP, val);\n+\n+\tdw_pcie_dbi_ro_wr_dis(pci);\n+}\n+\n void dw_pcie_setup(struct dw_pcie *pci)\n {\n \tu32 val;\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex 3e69ef60165b..6f741fd9d753 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -605,6 +605,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,\n \t\t\t\tu8 bar, size_t size);\n void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index);\n void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci);\n+void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on);\n void dw_pcie_setup(struct dw_pcie *pci);\n void dw_pcie_iatu_detect(struct dw_pcie *pci);\n int dw_pcie_edma_detect(struct dw_pcie *pci);\n", "prefixes": [ "v5", "2/3" ] }