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GET /api/1.1/patches/2229307/?format=api
{ "id": 2229307, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260428051216.2746030-1-sheetal@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428051216.2746030-1-sheetal@nvidia.com>", "date": "2026-04-28T05:12:16", "name": "ASoC: tegra: Add S8 PCM format support for MVC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e5a2f6f06c1fed5ee5484b68a521322ddfc0981", "submitter": { "id": 87986, "url": "http://patchwork.ozlabs.org/api/1.1/people/87986/?format=api", "name": "Sheetal", "email": "sheetal@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260428051216.2746030-1-sheetal@nvidia.com/mbox/", "series": [ { "id": 501762, "url": "http://patchwork.ozlabs.org/api/1.1/series/501762/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501762", "date": "2026-04-28T05:12:16", "name": "ASoC: tegra: Add S8 PCM format support for MVC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501762/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229307/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229307/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-14017-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=WL2P/NFh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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pr=C", "From": "Sheetal <sheetal@nvidia.com>", "To": "Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>", "CC": "Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>, \"Thierry\n Reding\" <thierry.reding@kernel.org>, Jonathan Hunter <jonathanh@nvidia.com>,\n\tKuninori Morimoto <kuninori.morimoto.gx@renesas.com>, Mohan Kumar\n\t<mkumard@nvidia.com>, Sameer Pujar <spujar@nvidia.com>,\n\t<linux-sound@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Anupama Kunkulagunta\n\t<akunkulagunt@nvidia.com>, Sheetal <sheetal@nvidia.com>", "Subject": "[PATCH] ASoC: tegra: Add S8 PCM format support for MVC", "Date": "Tue, 28 Apr 2026 05:12:16 +0000", "Message-ID": "<20260428051216.2746030-1-sheetal@nvidia.com>", "X-Mailer": "git-send-email 2.17.1", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3E:EE_|CY8PR12MB7684:EE_", "X-MS-Office365-Filtering-Correlation-Id": "27549537-c7a9-4ea9-a8a2-08dea4e4d045", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\t8tXBZtVEMnorALjj2RJkTM+l5l5emOgD19cyv0jUJFUbUNHPgCB3hti+a4D4P7ZKCrmgc9wEIRruLu5WFxjr9ffH7mI52qUL7o6mfNqBRk+qaY+Q6gkneuTrbM7azJIuH959t+gU/+z6l16wxoN9FMcbUFHxxZo5r6asujXDXVpGQ5PO9ZnGnifOueHmUF6EQxZZKBopd09CNqprkkrTKCzUhC9UoyETkr+ihwEEMuVNT80cvI7/WplZQ07U9V9OSfEQJGqgl59VzjFn3xMh0IHVV2DXD+igT992MinXCO1lOayRIkHQDq3+LAvoqnhk0Y9Vp+4QOP/0f4RhKfjpvo+yZaoLGGV/BtynG/yPEShtRggnOvC4C37ftwh8t4oHeD4+CsXv+BrVULrV3YDy3YcuDgmQX6WiKQgpCdURsM5xnvB4DX8vX2ie0E96rVq0iYLA8TeKJsZqk8BBpPxZU0R4SN9b5UhaYGoUlXP55/lq3rtGqutfK7J03ZeGwK7qmftMKHrV1++n6iRjBJK+sUkm/N+f4y9m4uaIaSW0zs1v2aR5n4TcdmdRr34fJeO64SNV2YXA6/GucckUNzlKjDPWasiH5TiIrBkOc360pUmYo1b5ofsKy0UdIsHdrb1wQlioPP4I/UjBlodWSY9tt7I9meLsMqeMt60slOYOQtlElcdkdKphfCecTExeFMW8R58bifo4byNkc4hM/mqhS7C6zCoUULGwfr1DCvUiIAiAOXywN5upG97sUa+5lJ+S6kdlWXgWjWgP+AjKi3Ftdw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(82310400026)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t1JwRxHSuOM/1XFtlCGYMEO5qmjNdmE24gZB+b4H5gVUxLWhul+obLF93F6Tlos3et3+l30M7txxR/+tbuAsMKinq1cgN/FRUVV5LUEgr8X2Iqn5DjjQLpFa4AGAEFck2qTje0T4BTwSy8sv7pbbYqv5vcAuV8f51gXDgE2I3A8NWvJoPoEQ02b30Om4+OeynSpIJrHkTVqgAtHhdNEKWqSJjl7lpARIisr6DLLWkXiagd8SfhtesDfFrJSRh+3TIh52BcTwtSZCyaumsgttzSySH28SxCq8ey5nbKY8etP2rROcQxhr8Q2gTaZZVy46nKCKkxzoDGzlJ3VCSaXDHlPRVhhlXJ7y+/B2rMPR7BcbVZ/dwZ5z34dw4Ys5yDG4bI8k2eV8ovxQetXZTFaGhXaWD5JF1YQJEFgUcsance0fyt6fNySCsRQpV4+dNxEZ3", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Apr 2026 05:12:58.5511\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 27549537-c7a9-4ea9-a8a2-08dea4e4d045", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE3E.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY8PR12MB7684" }, "content": "From: \"Anupama Kunkulagunta\" <akunkulagunt@nvidia.com>\n\nAdd handling for SNDRV_PCM_FORMAT_S8 in the MVC audio CIF\nconfiguration. This allows 8-bit PCM streams to be processed\nby setting the appropriate TEGRA_ACIF_BITS_8 format in the\nCIF configuration.\n\nSigned-off-by: Anupama Kunkulagunta <akunkulagunt@nvidia.com>\nSigned-off-by: Sheetal <sheetal@nvidia.com>\n---\n sound/soc/tegra/tegra210_mvc.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)", "diff": "diff --git a/sound/soc/tegra/tegra210_mvc.c b/sound/soc/tegra/tegra210_mvc.c\nindex 2c299704ef4f..07b88e5f18ae 100644\n--- a/sound/soc/tegra/tegra210_mvc.c\n+++ b/sound/soc/tegra/tegra210_mvc.c\n@@ -438,6 +438,9 @@ static int tegra210_mvc_set_audio_cif(struct tegra210_mvc *mvc,\n \tchannels = params_channels(params);\n \n \tswitch (params_format(params)) {\n+\tcase SNDRV_PCM_FORMAT_S8:\n+\t\taudio_bits = TEGRA_ACIF_BITS_8;\n+\t\tbreak;\n \tcase SNDRV_PCM_FORMAT_S16_LE:\n \t\taudio_bits = TEGRA_ACIF_BITS_16;\n \t\tbreak;\n", "prefixes": [] }