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GET /api/1.1/patches/2229298/?format=api
{ "id": 2229298, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229298/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com>", "date": "2026-04-28T03:48:19", "name": "[v2,6/9] ddr: altera: soc64: Add secure region support for ATF flow", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e773361b8441d13e93e48afb646c3126f645227f", "submitter": { "id": 90458, "url": "http://patchwork.ozlabs.org/api/1.1/people/90458/?format=api", "name": "YUSLAIMI, ALIF ZAKUAN", "email": "alif.zakuan.yuslaimi@altera.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com/mbox/", "series": [ { "id": 501758, "url": "http://patchwork.ozlabs.org/api/1.1/series/501758/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501758", "date": "2026-04-28T03:48:13", "name": "SoCFPGA: Update Boot Support for Stratix10 in U-Boot", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501758/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229298/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229298/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=tmfTFPzq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=altera.com; dmarc=pass action=none header.from=altera.com;\n dkim=pass header.d=altera.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=6lYo4yYq3AsLIj6owfnAbgzbCKvv34/teA3kijxNQcY=;\n b=tmfTFPzqXW2dc8ZvAATSSqtPg8wHnGrKWwsfUdXFNduT/Q1k5P8MhRuI/1j68QNuMZ2Mln8KMZta9pVks7q4O5YzJHusVU7a6xRNg2AdzHeR9vjqqs6GTm0/w5BabvfViKUs5dNB6jD0s3Fx/p5VAaFT7cJS6uuJcDIlrtrui7WBw4fGXABhIpllg+CNDXQ47ARYwIJXkHiOUKm3KppQUB+roa0+gmwragz3+yf+Y2xeriD0BnmG+sXAnEri9H6rv3I6o7DEea0GYOH+0ueMFbnF1cVGlQXVFf6vsSioErltaA4Onu1U64WPhmk6AanVrfHXMVREnqIIJI7WYVlecw==", "From": "alif.zakuan.yuslaimi@altera.com", "To": "u-boot@lists.denx.de", "Cc": "Tom Rini <trini@konsulko.com>, Marek Vasut <marex@denx.de>,\n Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,\n Tien Fong Chee <tien.fong.chee@altera.com>,\n Lukasz Majewski <lukma@denx.de>, Peng Fan <peng.fan@nxp.com>,\n Jaehoon Chung <jh80.chung@samsung.com>, Simon Glass <sjg@chromium.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Kory Maincent <kory.maincent@bootlin.com>, Yao Zi <me@ziyao.cc>,\n Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>", "Subject": "[PATCH v2 6/9] ddr: altera: soc64: Add secure region support for ATF\n flow", "Date": "Mon, 27 Apr 2026 20:48:19 -0700", "Message-ID": "<20260428034822.23756-7-alif.zakuan.yuslaimi@altera.com>", "X-Mailer": "git-send-email 2.43.7", "In-Reply-To": "<20260428034822.23756-1-alif.zakuan.yuslaimi@altera.com>", "References": "<20260428034822.23756-1-alif.zakuan.yuslaimi@altera.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR13CA0224.namprd13.prod.outlook.com\n (2603:10b6:a03:2c1::19) To PH7PR03MB7063.namprd03.prod.outlook.com\n (2603:10b6:510:2a4::6)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PH7PR03MB7063:EE_|SJ2PR03MB7403:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a47406cd-6a75-484c-7987-08dea4d9061a", "X-MS-Exchange-AtpMessageProperties": "SA", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|7416014|376014|1800799024|366016|22082099003|18002099003|56012099003|55112099003;", "X-Microsoft-Antispam-Message-Info": "\n XRMVw3ebe8lJCU0liibp7Y9Un05w75AvyhELEcT/OxymToplwIE12MV0I5pTb/rnt6iQGmteR6xF23iRePDPR36aLhFpB8IfZDovnY2xMv7FddJOj/XFJRmiy/L4z2nu2Xc/nE9ht9pJ57o/EFct0r3BDF8JAdYR+Tc34XeALR8DPD3Egs4d5S2skR0gpQ0JFDZDgwNa5i+q1/P+zStM2YjoAL3weywBvzU94oO//FTNEF96kn4Max52odHdeBoEs+6q0tYIWzGTbLSCxz6EaSqAocorwk5bMi3GlRu7JrtSabxB/6xNY4nqdykheuJfg5K/IW2lb7K05tyx/Q9Pn8LJAGL9OT9rm33QtE+BR4IOowopFWI9eeKzIeQm6Xs0qE0vZQCmJpFvLoVhE51Fsi+9El5kkOn0NjK/lpK+LNaiQGs1Rk1oFe0ek/MACK7zL3EvxRPZaRonTGiv0nF1uhcfG/KyWIg+gHOKYM3J2+Hc/aUuYoBfAe+9epLx7XXwDY901lmEma5YdeF+j+rLtKG7QtB2MQj7mnAjPXE1BEVkCzT96aiVwMVzpIMKZVCh02CMQGWe4UFXBJeMh3FLfZ1ulGDOrg6MuPg0ihtuVh7eAQzjgdbu1NVAbC5ZyhcSk7cbPuOC2xX4omlGGHNeyO7ZViHiL+HvNr2fxNXWC96hRPf0tgWEh6tHX53z2j/JfQKNAqW/uSso7pMkl+cW/h9JsuFFGrYqbCW2SAy6rPE=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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The ARM Trusted Firmware (ATF)\nimage is located in this first 1 MiB memory region. So, this can prevent\nsoftware executing at non-secure state EL0-EL2 and non-secure masters\naccess to secure region.\n\nAdd common function for firewall setup and reuse for all SoC64 devices.\n\nSigned-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>\n---\n drivers/ddr/altera/sdram_s10.c | 16 ++--------------\n 1 file changed, 2 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c\nindex 1497a8e4aab..aed53ae58eb 100644\n--- a/drivers/ddr/altera/sdram_s10.c\n+++ b/drivers/ddr/altera/sdram_s10.c\n@@ -78,20 +78,6 @@ int sdram_mmr_init_full(struct udevice *dev)\n \tphys_size_t hw_size;\n \tstruct bd_info bd = {0};\n \n-\t/* this enables nonsecure access to DDR */\n-\t/* mpuregion0addr_limit */\n-\tFW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);\n-\tFW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);\n-\n-\t/* nonmpuregion0addr_limit */\n-\tFW_MPU_DDR_SCR_WRITEL(0xFFFF0000,\n-\t\t\t FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);\n-\tFW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);\n-\n-\t/* Enable mpuregion0enable and nonmpuregion0enable */\n-\tFW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,\n-\t\t\t FW_MPU_DDR_SCR_EN_SET);\n-\n \t/* Ensure HMC clock is running */\n \tif (poll_hmc_clock_status()) {\n \t\tputs(\"DDR: Error as HMC clock not running\\n\");\n@@ -284,6 +270,8 @@ int sdram_mmr_init_full(struct udevice *dev)\n \n \tsdram_size_check(&bd);\n \n+\tsdram_set_firewall(&bd);\n+\n \tpriv->info.base = bd.bi_dram[0].start;\n \tpriv->info.size = gd->ram_size;\n \n", "prefixes": [ "v2", "6/9" ] }