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{
    "id": 2229295,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229295/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-2-alif.zakuan.yuslaimi@altera.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
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        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20260428034822.23756-2-alif.zakuan.yuslaimi@altera.com>",
    "date": "2026-04-28T03:48:14",
    "name": "[v2,1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "5c7931b211d6d4ab1051879d504a22fe3118b5bd",
    "submitter": {
        "id": 90458,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/90458/?format=api",
        "name": "YUSLAIMI, ALIF ZAKUAN",
        "email": "alif.zakuan.yuslaimi@altera.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428034822.23756-2-alif.zakuan.yuslaimi@altera.com/mbox/",
    "series": [
        {
            "id": 501758,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501758/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501758",
            "date": "2026-04-28T03:48:13",
            "name": "SoCFPGA: Update Boot Support for Stratix10 in U-Boot",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/501758/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2229295/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2229295/checks/",
    "tags": {},
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        "From": "alif.zakuan.yuslaimi@altera.com",
        "To": "u-boot@lists.denx.de",
        "Cc": "Tom Rini <trini@konsulko.com>, Marek Vasut <marex@denx.de>,\n Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,\n Tien Fong Chee <tien.fong.chee@altera.com>,\n Lukasz Majewski <lukma@denx.de>, Peng Fan <peng.fan@nxp.com>,\n Jaehoon Chung <jh80.chung@samsung.com>, Simon Glass <sjg@chromium.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Kory Maincent <kory.maincent@bootlin.com>, Yao Zi <me@ziyao.cc>,\n Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>",
        "Subject": "[PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream\n Linux DT config",
        "Date": "Mon, 27 Apr 2026 20:48:14 -0700",
        "Message-ID": "<20260428034822.23756-2-alif.zakuan.yuslaimi@altera.com>",
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    "content": "From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>\n\nMigrate the legacy Stratix10 platform to use the upstream Linux device tree\nconfiguration. This helps reduce maintenance overhead and aligns U-Boot\nwith the Linux kernel's DTS hierarchy and naming conventions.\n\nThis change improves consistency between U-Boot and Linux by removing\ncustom/legacy DTS handling and instead relying on the standardized\ndefinitions provided by the upstream Linux DTS.\n\nSigned-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>\n---\n arch/arm/dts/Makefile                         |   3 +-\n arch/arm/dts/socfpga_stratix10-u-boot.dtsi    | 158 +++++++\n arch/arm/dts/socfpga_stratix10.dtsi           | 430 ------------------\n .../dts/socfpga_stratix10_socdk-u-boot.dtsi   | 143 +++++-\n arch/arm/dts/socfpga_stratix10_socdk.dts      | 143 ------\n configs/socfpga_stratix10_defconfig           |   3 +-\n 6 files changed, 286 insertions(+), 594 deletions(-)\n delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi\n delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts",
    "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex bff341d6118..2832123218f 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -460,8 +460,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=\t\t\t\t\\\n \tsocfpga_cyclone5_vining_fpga.dtb\t\t\\\n \tsocfpga_cyclone5_ac501soc.dtb\t\t\t\\\n \tsocfpga_cyclone5_ac550soc.dtb\t\t\t\\\n-\tsocfpga_n5x_socdk.dtb\t\t\t\t\\\n-\tsocfpga_stratix10_socdk.dtb\n+\tsocfpga_n5x_socdk.dtb\n \n dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb\t\\\n \tdra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb\ndiff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi\nindex 3e3a3780469..a3b4c0564f9 100644\n--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi\n+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi\n@@ -3,6 +3,164 @@\n  * U-Boot additions\n  *\n  * Copyright (C) 2020 Intel Corporation <www.intel.com>\n+ * Copyright (C) 2026 Altera Corporation <www.altera.com>\n  */\n \n #include \"socfpga_soc64_fit-u-boot.dtsi\"\n+\n+/{\n+\taliases {\n+\t\tspi0 = &qspi;\n+\t\ti2c0 = &i2c1;\n+\t\tfreeze_br0 = &freeze_controller;\n+\t};\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tbootph-all;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,armv8-pmuv3\";\n+\t};\n+\n+\tsoc@0 {\n+\t\tbootph-all;\n+\n+\t\tfreeze_controller: freeze_controller@f9000450 {\n+\t\t\tcompatible = \"altr,freeze-bridge-controller\";\n+\t\t\treg = <0xf9000450 0x00000010>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+};\n+\n+&clkmgr {\n+\tbootph-all;\n+};\n+\n+&gmac0 {\n+\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\treset-names = \"stmmaceth\", \"stmmaceth-ocp\";\n+\tclocks = <&clkmgr STRATIX10_EMAC0_CLK>;\n+\tclock-names = \"stmmaceth\";\n+\t/* PHY delays is configured via skew properties */\n+\tphy-mode = \"rgmii\";\n+\tmax-frame-size = <3800>;\n+\tstatus = \"okay\";\n+\n+\tmdio0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t};\n+};\n+\n+&gmac1 {\n+\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\treset-names = \"stmmaceth\", \"stmmaceth-ocp\";\n+\taltr,sysmgr-syscon = <&sysmgr 0x48 0>;\n+\tclocks = <&clkmgr STRATIX10_EMAC1_CLK>;\n+\tclock-names = \"stmmaceth\";\n+\tstatus = \"disabled\";\n+};\n+\n+&gmac2 {\n+\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\treset-names = \"stmmaceth\", \"stmmaceth-ocp\";\n+\taltr,sysmgr-syscon = <&sysmgr 0x4c 0>;\n+\tclocks = <&clkmgr STRATIX10_EMAC2_CLK>;\n+\tclock-names = \"stmmaceth\";\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c0 {\n+\treset-names = \"i2c\";\n+};\n+\n+&i2c1 {\n+\treset-names = \"i2c\";\n+\tstatus = \"okay\";\n+};\n+\n+&i2c2 {\n+\treset-names = \"i2c\";\n+};\n+\n+&i2c3 {\n+\treset-names = \"i2c\";\n+};\n+\n+&mmc {\n+\tresets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;\n+\tfifo-mode;\n+};\n+\n+&porta {\n+\tbank-name = \"porta\";\n+};\n+\n+&portb {\n+\tbank-name = \"portb\";\n+};\n+\n+&qspi {\n+\tbootph-all;\n+\tcompatible = \"cdns,qspi-nor\";\n+\tflash0: flash@0 {\n+\t};\n+};\n+\n+&flash0 {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tcompatible = \"jedec,spi-nor\";\n+};\n+\n+&rst {\n+\tcompatible = \"altr,rst-mgr\";\n+\taltr,modrst-offset = <0x20>;\n+\tbootph-all;\n+};\n+\n+&sdr {\n+\tcompatible = \"altr,sdr-ctl-s10\";\n+\treg = <0xf8000400 0x80>,\n+\t      <0xf8010000 0x190>,\n+\t      <0xf8011000 0x500>;\n+\tresets = <&rst DDRSCH_RESET>;\n+\tbootph-all;\n+};\n+\n+&uart0 {\n+\tbootph-all;\n+\tclock-frequency = <100000000>;\n+};\n+\n+&watchdog0 {\n+\tbootph-all;\n+};\n+\n+&usb0 {\n+\tcompatible = \"snps,dwc2\";\n+};\n+\n+&usb1 {\n+\tcompatible = \"snps,dwc2\";\n+};\n+\n+&spi0 {\n+\tcompatible = \"intel,stratix10-spi\",\n+\t\t     \"snps,dw-apb-ssi-4.00a\", \"snps,dw-apb-ssi\";\n+};\n+\n+&spi1 {\n+\tcompatible = \"intel,stratix10-spi\",\n+\t\t     \"snps,dw-apb-ssi-4.00a\", \"snps,dw-apb-ssi\";\n+};\n+\n+&binman {\n+\t/delete-node/ kernel;\n+};\ndiff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi\ndeleted file mode 100644\nindex ea80d1bed15..00000000000\n--- a/arch/arm/dts/socfpga_stratix10.dtsi\n+++ /dev/null\n@@ -1,430 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-/*\n- * Copyright (C) 2018 Intel Corporation\n- */\n-\n-/dts-v1/;\n-#include <dt-bindings/reset/altr,rst-mgr-s10.h>\n-#include <dt-bindings/gpio/gpio.h>\n-\n-/ {\n-\tcompatible = \"altr,socfpga-stratix10\";\n-\t#address-cells = <2>;\n-\t#size-cells = <2>;\n-\n-\tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcpu0: cpu@0 {\n-\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tenable-method = \"psci\";\n-\t\t\treg = <0x0>;\n-\t\t};\n-\n-\t\tcpu1: cpu@1 {\n-\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tenable-method = \"psci\";\n-\t\t\treg = <0x1>;\n-\t\t};\n-\n-\t\tcpu2: cpu@2 {\n-\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tenable-method = \"psci\";\n-\t\t\treg = <0x2>;\n-\t\t};\n-\n-\t\tcpu3: cpu@3 {\n-\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tenable-method = \"psci\";\n-\t\t\treg = <0x3>;\n-\t\t};\n-\t};\n-\n-\tpmu {\n-\t\tcompatible = \"arm,armv8-pmuv3\";\n-\t\tinterrupts = <0 120 8>,\n-\t\t\t     <0 121 8>,\n-\t\t\t     <0 122 8>,\n-\t\t\t     <0 123 8>;\n-\t\tinterrupt-affinity = <&cpu0>,\n-\t\t\t\t     <&cpu1>,\n-\t\t\t\t     <&cpu2>,\n-\t\t\t\t     <&cpu3>;\n-\t\tinterrupt-parent = <&intc>;\n-\t};\n-\n-\tpsci {\n-\t\tcompatible = \"arm,psci-0.2\";\n-\t\tmethod = \"smc\";\n-\t};\n-\n-\tintc: intc@fffc1000 {\n-\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n-\t\t#interrupt-cells = <3>;\n-\t\tinterrupt-controller;\n-\t\treg = <0x0 0xfffc1000 0x0 0x1000>,\n-\t\t      <0x0 0xfffc2000 0x0 0x2000>,\n-\t\t      <0x0 0xfffc4000 0x0 0x2000>,\n-\t\t      <0x0 0xfffc6000 0x0 0x2000>;\n-\t};\n-\n-\tsoc {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tcompatible = \"simple-bus\";\n-\t\tdevice_type = \"soc\";\n-\t\tinterrupt-parent = <&intc>;\n-\t\tranges = <0 0 0 0xffffffff>;\n-\t\tbootph-all;\n-\n-\t\tclkmgr: clkmgr@ffd10000 {\n-\t\t\tcompatible = \"altr,clk-mgr\";\n-\t\t\treg = <0xffd10000 0x1000>;\n-\t\t};\n-\n-\t\tgmac0: ethernet@ff800000 {\n-\t\t\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n-\t\t\treg = <0xff800000 0x2000>;\n-\t\t\tinterrupts = <0 90 4>;\n-\t\t\tinterrupt-names = \"macirq\";\n-\t\t\tmac-address = [00 00 00 00 00 00];\n-\t\t\tresets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n-\t\t\taltr,sysmgr-syscon = <&sysmgr 0x44 0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tgmac1: ethernet@ff802000 {\n-\t\t\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n-\t\t\treg = <0xff802000 0x2000>;\n-\t\t\tinterrupts = <0 91 4>;\n-\t\t\tinterrupt-names = \"macirq\";\n-\t\t\tmac-address = [00 00 00 00 00 00];\n-\t\t\tresets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n-\t\t\taltr,sysmgr-syscon = <&sysmgr 0x48 0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tgmac2: ethernet@ff804000 {\n-\t\t\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n-\t\t\treg = <0xff804000 0x2000>;\n-\t\t\tinterrupts = <0 92 4>;\n-\t\t\tinterrupt-names = \"macirq\";\n-\t\t\tmac-address = [00 00 00 00 00 00];\n-\t\t\tresets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n-\t\t\taltr,sysmgr-syscon = <&sysmgr 0x4c 0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tgpio0: gpio@ffc03200 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,dw-apb-gpio\";\n-\t\t\treg = <0xffc03200 0x100>;\n-\t\t\tresets = <&rst GPIO0_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\n-\t\t\tporta: gpio-controller@0 {\n-\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tsnps,nr-gpios = <24>;\n-\t\t\t\treg = <0>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tinterrupts = <0 110 4>;\n-\t\t\t\tbank-name = \"porta\";\n-\t\t\t};\n-\t\t};\n-\n-\t\tgpio1: gpio@ffc03300 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,dw-apb-gpio\";\n-\t\t\treg = <0xffc03300 0x100>;\n-\t\t\tresets = <&rst GPIO1_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\n-\t\t\tportb: gpio-controller@0 {\n-\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n-\t\t\t\tgpio-controller;\n-\t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tsnps,nr-gpios = <24>;\n-\t\t\t\treg = <0>;\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#interrupt-cells = <2>;\n-\t\t\t\tinterrupts = <0 111 4>;\n-\t\t\t\tbank-name = \"portb\";\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c0: i2c@ffc02800 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,designware-i2c\";\n-\t\t\treg = <0xffc02800 0x100>;\n-\t\t\tinterrupts = <0 103 4>;\n-\t\t\tresets = <&rst I2C0_RESET>;\n-\t\t\treset-names = \"i2c\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\ti2c1: i2c@ffc02900 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,designware-i2c\";\n-\t\t\treg = <0xffc02900 0x100>;\n-\t\t\tinterrupts = <0 104 4>;\n-\t\t\tresets = <&rst I2C1_RESET>;\n-\t\t\treset-names = \"i2c\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\ti2c2: i2c@ffc02a00 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,designware-i2c\";\n-\t\t\treg = <0xffc02a00 0x100>;\n-\t\t\tinterrupts = <0 105 4>;\n-\t\t\tresets = <&rst I2C2_RESET>;\n-\t\t\treset-names = \"i2c\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\ti2c3: i2c@ffc02b00 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,designware-i2c\";\n-\t\t\treg = <0xffc02b00 0x100>;\n-\t\t\tinterrupts = <0 106 4>;\n-\t\t\tresets = <&rst I2C3_RESET>;\n-\t\t\treset-names = \"i2c\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\ti2c4: i2c@ffc02c00 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"snps,designware-i2c\";\n-\t\t\treg = <0xffc02c00 0x100>;\n-\t\t\tinterrupts = <0 107 4>;\n-\t\t\tresets = <&rst I2C4_RESET>;\n-\t\t\treset-names = \"i2c\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tmmc: dwmmc0@ff808000 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"altr,socfpga-dw-mshc\";\n-\t\t\treg = <0xff808000 0x1000>;\n-\t\t\tinterrupts = <0 96 4>;\n-\t\t\tfifo-depth = <0x400>;\n-\t\t\tresets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;\n-\t\t\tbootph-all;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tnand: nand@ffb90000 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"altr,socfpga-denali-nand\";\n-\t\t\treg = <0xffb90000 0x10000>,\n-\t\t\t      <0xffb80000 0x1000>;\n-\t\t\treg-names = \"nand_data\", \"denali_reg\";\n-\t\t\tinterrupts = <0 97 4>;\n-\t\t\tresets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tocram: sram@ffe00000 {\n-\t\t\tcompatible = \"mmio-sram\";\n-\t\t\treg = <0xffe00000 0x100000>;\n-\t\t};\n-\n-\t\tqspi: spi@ff8d2000 {\n-\t\t\tcompatible = \"cdns,qspi-nor\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\treg = <0xff8d2000 0x100>,\n-\t\t\t      <0xff900000 0x100000>;\n-\t\t\tinterrupts = <0 3 4>;\n-\t\t\tcdns,fifo-depth = <128>;\n-\t\t\tcdns,fifo-width = <4>;\n-\t\t\tcdns,trigger-address = <0x00000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\trst: rstmgr@ffd11000 {\n-\t\t\t#reset-cells = <1>;\n-\t\t\tcompatible = \"altr,rst-mgr\";\n-\t\t\treg = <0xffd11000 0x1000>;\n-\t\t\taltr,modrst-offset = <0x20>;\n-\t\t\tbootph-all;\n-\t\t};\n-\n-\t\tsdr: sdr@f8000400 {\n-\t\t\t compatible = \"altr,sdr-ctl-s10\";\n-\t\t\t reg = <0xf8000400 0x80>,\n-\t\t\t       <0xf8010000 0x190>,\n-\t\t\t       <0xf8011000 0x500>;\n-\t\t\t resets = <&rst DDRSCH_RESET>;\n-\t\t\t bootph-all;\n-\t\t };\n-\n-\t\tspi0: spi@ffda4000 {\n-\t\t\tcompatible = \"intel,stratix10-spi\",\n-\t\t\t\t     \"snps,dw-apb-ssi-4.00a\", \"snps,dw-apb-ssi\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\treg = <0xffda4000 0x1000>;\n-\t\t\tinterrupts = <0 99 4>;\n-\t\t\tresets = <&rst SPIM0_RESET>;\n-\t\t\treg-io-width = <4>;\n-\t\t\tnum-chipselect = <4>;\n-\t\t\tbus-num = <0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tspi1: spi@ffda5000 {\n-\t\t\tcompatible = \"intel,stratix10-spi\",\n-\t\t\t\t     \"snps,dw-apb-ssi-4.00a\", \"snps,dw-apb-ssi\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\treg = <0xffda5000 0x1000>;\n-\t\t\tinterrupts = <0 100 4>;\n-\t\t\tresets = <&rst SPIM1_RESET>;\n-\t\t\treg-io-width = <4>;\n-\t\t\tnum-chipselect = <4>;\n-\t\t\tbus-num = <0>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tsysmgr: sysmgr@ffd12000 {\n-\t\t\tcompatible = \"altr,sys-mgr\", \"syscon\";\n-\t\t\treg = <0xffd12000 0x1000>;\n-\t\t};\n-\n-\t\t/* Local timer */\n-\t\ttimer {\n-\t\t\tcompatible = \"arm,armv8-timer\";\n-\t\t\tinterrupts = <1 13 0xf08>,\n-\t\t\t\t     <1 14 0xf08>,\n-\t\t\t\t     <1 11 0xf08>,\n-\t\t\t\t     <1 10 0xf08>;\n-\t\t};\n-\n-\t\ttimer0: timer0@ffc03000 {\n-\t\t\tcompatible = \"snps,dw-apb-timer\";\n-\t\t\tinterrupts = <0 113 4>;\n-\t\t\treg = <0xffc03000 0x100>;\n-\t\t};\n-\n-\t\ttimer1: timer1@ffc03100 {\n-\t\t\tcompatible = \"snps,dw-apb-timer\";\n-\t\t\tinterrupts = <0 114 4>;\n-\t\t\treg = <0xffc03100 0x100>;\n-\t\t};\n-\n-\t\ttimer2: timer2@ffd00000 {\n-\t\t\tcompatible = \"snps,dw-apb-timer\";\n-\t\t\tinterrupts = <0 115 4>;\n-\t\t\treg = <0xffd00000 0x100>;\n-\t\t};\n-\n-\t\ttimer3: timer3@ffd00100 {\n-\t\t\tcompatible = \"snps,dw-apb-timer\";\n-\t\t\tinterrupts = <0 116 4>;\n-\t\t\treg = <0xffd00100 0x100>;\n-\t\t};\n-\n-\t\tuart0: serial0@ffc02000 {\n-\t\t\tcompatible = \"snps,dw-apb-uart\";\n-\t\t\treg = <0xffc02000 0x100>;\n-\t\t\tinterrupts = <0 108 4>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n-\t\t\tresets = <&rst UART0_RESET>;\n-\t\t\tclock-frequency = <100000000>;\n-\t\t\tbootph-all;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tuart1: serial1@ffc02100 {\n-\t\t\tcompatible = \"snps,dw-apb-uart\";\n-\t\t\treg = <0xffc02100 0x100>;\n-\t\t\tinterrupts = <0 109 4>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n-\t\t\tresets = <&rst UART1_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusbphy0: usbphy@0 {\n-\t\t\t#phy-cells = <0>;\n-\t\t\tcompatible = \"usb-nop-xceiv\";\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\n-\t\tusb0: usb@ffb00000 {\n-\t\t\tcompatible = \"snps,dwc2\";\n-\t\t\treg = <0xffb00000 0x40000>;\n-\t\t\tinterrupts = <0 93 4>;\n-\t\t\tphys = <&usbphy0>;\n-\t\t\tphy-names = \"usb2-phy\";\n-\t\t\tresets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;\n-\t\t\treset-names = \"dwc2\", \"dwc2-ecc\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusb1: usb@ffb40000 {\n-\t\t\tcompatible = \"snps,dwc2\";\n-\t\t\treg = <0xffb40000 0x40000>;\n-\t\t\tinterrupts = <0 94 4>;\n-\t\t\tphys = <&usbphy0>;\n-\t\t\tphy-names = \"usb2-phy\";\n-\t\t\tresets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;\n-\t\t\treset-names = \"dwc2\", \"dwc2-ecc\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\twatchdog0: watchdog@ffd00200 {\n-\t\t\tcompatible = \"snps,dw-wdt\";\n-\t\t\treg = <0xffd00200 0x100>;\n-\t\t\tinterrupts = <0 117 4>;\n-\t\t\tresets = <&rst WATCHDOG0_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\twatchdog1: watchdog@ffd00300 {\n-\t\t\tcompatible = \"snps,dw-wdt\";\n-\t\t\treg = <0xffd00300 0x100>;\n-\t\t\tinterrupts = <0 118 4>;\n-\t\t\tresets = <&rst WATCHDOG1_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\twatchdog2: watchdog@ffd00400 {\n-\t\t\tcompatible = \"snps,dw-wdt\";\n-\t\t\treg = <0xffd00400 0x100>;\n-\t\t\tinterrupts = <0 125 4>;\n-\t\t\tresets = <&rst WATCHDOG2_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\twatchdog3: watchdog@ffd00500 {\n-\t\t\tcompatible = \"snps,dw-wdt\";\n-\t\t\treg = <0xffd00500 0x100>;\n-\t\t\tinterrupts = <0 126 4>;\n-\t\t\tresets = <&rst WATCHDOG3_RESET>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\t};\n-};\ndiff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi\nindex ef0df769762..da19943ec3b 100644\n--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi\n+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi\n@@ -3,47 +3,154 @@\n  * U-Boot additions\n  *\n  * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>\n+ * Copyright (C) 2026 Altera Corporation <www.altera.com>\n  */\n \n #include \"socfpga_stratix10-u-boot.dtsi\"\n \n /{\n-\taliases {\n-\t\tspi0 = &qspi;\n-\t\tfreeze_br0 = &freeze_controller;\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t\tu-boot,spl-boot-order = &mmc,&flash0,&nand;\n \t};\n \n-\tsoc {\n-\t\tfreeze_controller: freeze_controller@f9000450 {\n-\t\t\tcompatible = \"altr,freeze-bridge-controller\";\n-\t\t\treg = <0xf9000450 0x00000010>;\n-\t\t\tstatus = \"disabled\";\n+\tmemory@0 {\n+\t\t/* 4GB */\n+\t\treg = <0 0x00000000 0 0x80000000>,\n+\t\t      <1 0x80000000 0 0x80000000>;\n+\t};\n+};\n+\n+&qspi {\n+\tstatus = \"okay\";\n+};\n+\n+&gmac0 {\n+\tmdio0 {\n+\t\tethernet_phy0: ethernet-phy@0 {\n+\t\t\treg = <4>;\n+\t\t\ttxd0-skew-ps = <0>; /* -420ps */\n+\t\t\ttxd1-skew-ps = <0>; /* -420ps */\n+\t\t\ttxd2-skew-ps = <0>; /* -420ps */\n+\t\t\ttxd3-skew-ps = <0>; /* -420ps */\n+\t\t\trxd0-skew-ps = <420>; /* 0ps */\n+\t\t\trxd1-skew-ps = <420>; /* 0ps */\n+\t\t\trxd2-skew-ps = <420>; /* 0ps */\n+\t\t\trxd3-skew-ps = <420>; /* 0ps */\n+\t\t\ttxen-skew-ps = <0>; /* -420ps */\n+\t\t\ttxc-skew-ps = <900>; /* 0ps */\n+\t\t\trxdv-skew-ps = <420>; /* 0ps */\n+\t\t\trxc-skew-ps = <1680>; /* 780ps */\n \t\t};\n \t};\n };\n \n-&clkmgr {\n+&mmc {\n+\tdrvsel = <3>;\n+\tsmplsel = <2>;\n \tbootph-all;\n };\n \n &qspi {\n-\tstatus = \"okay\";\n-\tbootph-all;\n+\t/delete-property/ clocks;\n };\n \n &flash0 {\n-\tcompatible = \"jedec,spi-nor\";\n-\tspi-max-frequency = <100000000>;\n+\treg = <0>;\n \tspi-tx-bus-width = <4>;\n \tspi-rx-bus-width = <4>;\n \tbootph-all;\n+\n+\tm25p,fast-read;\n+\tcdns,page-size = <256>;\n+\tcdns,block-size = <16>;\n+\tcdns,tshsl-ns = <50>;\n+\tcdns,tsd2d-ns = <50>;\n+\tcdns,tchsh-ns = <4>;\n+\tcdns,tslch-ns = <4>;\n+\t/delete-property/ cdns,read-delay;\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tqspi_boot: partition@0 {\n+\t\t\tlabel = \"u-boot\";\n+\t\t\treg = <0x0 0x04200000>;\n+\t\t};\n+\n+\t\troot: partition@4200000 {\n+\t\t\tlabel = \"root\";\n+\t\t\treg = <0x04200000 0x0BE00000>;\n+\t\t};\n+\t};\n };\n \n-&sysmgr {\n-\tbootph-all;\n+&fdt_0_blob {\n+\tfilename = \"dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dtb\";\n };\n \n-&watchdog0 {\n-\tstatus = \"okay\";\n-\tbootph-all;\n+&images {\n+\tfdt-1 {\n+\t\tdescription = \"socfpga_socdk_nand\";\n+\t\ttype = \"flat_dt\";\n+\t\tcompression = \"none\";\n+\t\tfdt_1_blob: blob-ext {\n+\t\t\tfilename = \"dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dtb\";\n+\t\t};\n+\t\thash {\n+\t\t\talgo = \"crc32\";\n+\t\t};\n+\t};\n+\n+\tfdt-2 {\n+\t\tdescription = \"socfpga_socdk_emmc\";\n+\t\ttype = \"flat_dt\";\n+\t\tcompression = \"none\";\n+\t\tfdt_2_blob: blob-ext {\n+\t\t\tfilename = \"dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_emmc.dtb\";\n+\t\t};\n+\t\thash {\n+\t\t\talgo = \"crc32\";\n+\t\t};\n+\t};\n+};\n+\n+&board_config {\n+\tboard-1 {\n+\t\tdescription = \"board_1\";\n+\t\tfirmware = \"atf\";\n+\t\tloadables = \"uboot\";\n+\t\tfdt = \"fdt-1\";\n+\t\tsignature {\n+\t\t\talgo = \"crc32\";\n+\t\t\tkey-name-hint = \"dev\";\n+\t\t\tsign-images = \"atf\", \"uboot\", \"fdt-1\";\n+\t\t};\n+\t};\n+\n+\tboard-2 {\n+\t\tdescription = \"board_2\";\n+\t\tfirmware = \"atf\";\n+\t\tloadables = \"uboot\";\n+\t\tfdt = \"fdt-2\";\n+\t\tsignature {\n+\t\t\talgo = \"crc32\";\n+\t\t\tkey-name-hint = \"dev\";\n+\t\t\tsign-images = \"atf\", \"uboot\", \"fdt-2\";\n+\t\t};\n+\t};\n+\n+\tboard-4 {\n+\t\tdescription = \"board_4\";\n+\t\tfirmware = \"atf\";\n+\t\tloadables = \"uboot\";\n+\t\tfdt = \"fdt-0\";\n+\t\tsignature {\n+\t\t\talgo = \"crc32\";\n+\t\t\tkey-name-hint = \"dev\";\n+\t\t\tsign-images = \"atf\", \"uboot\", \"fdt-0\";\n+\t\t};\n+\t};\n };\ndiff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts\ndeleted file mode 100644\nindex 864f4093ef8..00000000000\n--- a/arch/arm/dts/socfpga_stratix10_socdk.dts\n+++ /dev/null\n@@ -1,143 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-/*\n- * Copyright (C) 2018 Intel Corporation\n- */\n-\n-#include \"socfpga_stratix10.dtsi\"\n-\n-/ {\n-\tmodel = \"SoCFPGA Stratix 10 SoCDK\";\n-\n-\taliases {\n-\t\tethernet0 = &gmac0;\n-\t\ti2c0 = &i2c1;\n-\t\tserial0 = &uart0;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = \"serial0:115200n8\";\n-\t};\n-\n-\tleds {\n-\t\tcompatible = \"gpio-leds\";\n-\t\thps0 {\n-\t\t\tlabel = \"hps_led0\";\n-\t\t\tgpios = <&portb 20 GPIO_ACTIVE_HIGH>;\n-\t\t};\n-\n-\t\thps1 {\n-\t\t\tlabel = \"hps_led1\";\n-\t\t\tgpios = <&portb 19 GPIO_ACTIVE_HIGH>;\n-\t\t};\n-\n-\t\thps2 {\n-\t\t\tlabel = \"hps_led2\";\n-\t\t\tgpios = <&portb 21 GPIO_ACTIVE_HIGH>;\n-\t\t};\n-\t};\n-\n-\tmemory {\n-\t\t#address-cells = <2>;\n-\t\t#size-cells = <2>;\n-\t\tdevice_type = \"memory\";\n-\t\t/* 4GB */\n-\t\treg = <0 0x00000000 0 0x80000000>,\n-\t\t      <1 0x80000000 0 0x80000000>;\n-\t\tbootph-all;\n-\t};\n-};\n-\n-&gpio1 {\n-\tstatus = \"okay\";\n-};\n-\n-&gmac0 {\n-\tstatus = \"okay\";\n-\tphy-mode = \"rgmii\";\n-\tphy-handle = <&phy0>;\n-\n-\tmax-frame-size = <3800>;\n-\n-\tmdio0 {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tcompatible = \"snps,dwmac-mdio\";\n-\t\tphy0: ethernet-phy@0 {\n-\t\t\treg = <4>;\n-\n-\t\t\ttxd0-skew-ps = <0>; /* -420ps */\n-\t\t\ttxd1-skew-ps = <0>; /* -420ps */\n-\t\t\ttxd2-skew-ps = <0>; /* -420ps */\n-\t\t\ttxd3-skew-ps = <0>; /* -420ps */\n-\t\t\trxd0-skew-ps = <420>; /* 0ps */\n-\t\t\trxd1-skew-ps = <420>; /* 0ps */\n-\t\t\trxd2-skew-ps = <420>; /* 0ps */\n-\t\t\trxd3-skew-ps = <420>; /* 0ps */\n-\t\t\ttxen-skew-ps = <0>; /* -420ps */\n-\t\t\ttxc-skew-ps = <900>; /* 0ps */\n-\t\t\trxdv-skew-ps = <420>; /* 0ps */\n-\t\t\trxc-skew-ps = <1680>; /* 780ps */\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tstatus = \"okay\";\n-};\n-\n-&mmc {\n-\tstatus = \"okay\";\n-\tcap-sd-highspeed;\n-\tcap-mmc-highspeed;\n-\tbroken-cd;\n-\tbus-width = <4>;\n-\tdrvsel = <3>;\n-\tsmplsel = <2>;\n-};\n-\n-&qspi {\n-\tflash0: flash@0 {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tcompatible = \"n25q00a\";\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <50000000>;\n-\n-\t\tm25p,fast-read;\n-\t\tcdns,page-size = <256>;\n-\t\tcdns,block-size = <16>;\n-\t\tcdns,read-delay = <1>;\n-\t\tcdns,tshsl-ns = <50>;\n-\t\tcdns,tsd2d-ns = <50>;\n-\t\tcdns,tchsh-ns = <4>;\n-\t\tcdns,tslch-ns = <4>;\n-\n-\t\tpartitions {\n-\t\t\tcompatible = \"fixed-partitions\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\n-\t\t\tqspi_boot: partition@0 {\n-\t\t\t\tlabel = \"Boot and fpga data\";\n-\t\t\t\treg = <0x0 0x4000000>;\n-\t\t\t};\n-\n-\t\t\tqspi_rootfs: partition@4000000 {\n-\t\t\t\tlabel = \"Root Filesystem - JFFS2\";\n-\t\t\t\treg = <0x4000000 0x4000000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&uart0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0 {\n-\tstatus = \"okay\";\n-};\n-\n-&watchdog0 {\n-\tstatus = \"okay\";\n-};\ndiff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig\nindex e360048078c..ef21dc92493 100644\n--- a/configs/socfpga_stratix10_defconfig\n+++ b/configs/socfpga_stratix10_defconfig\n@@ -10,7 +10,8 @@ CONFIG_SF_DEFAULT_MODE=0x2003\n CONFIG_ENV_SIZE=0x1000\n CONFIG_ENV_OFFSET=0x200\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_stratix10_socdk\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"altera/socfpga_stratix10_socdk\"\n+CONFIG_OF_UPSTREAM=y\n CONFIG_DM_RESET=y\n CONFIG_SPL_STACK=0xffe3f000\n CONFIG_SPL_TEXT_BASE=0xFFE00000\n",
    "prefixes": [
        "v2",
        "1/9"
    ]
}