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{ "id": 2229269, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229269/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/e179a50b-7829-49ec-84fe-e342bc37100a@yahoo.co.jp/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<e179a50b-7829-49ec-84fe-e342bc37100a@yahoo.co.jp>", "date": "2026-04-27T23:58:40", "name": "xtensa: Apply further improvement to xtensa_legitimize_address()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "42d8fbdd5295c17eb9d4364d935e702648101668", "submitter": { "id": 83997, "url": "http://patchwork.ozlabs.org/api/1.1/people/83997/?format=api", "name": "Takayuki 'January June' Suwa", "email": "jjsuwa_sys3175@yahoo.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/e179a50b-7829-49ec-84fe-e342bc37100a@yahoo.co.jp/mbox/", "series": [ { "id": 501746, "url": "http://patchwork.ozlabs.org/api/1.1/series/501746/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501746", "date": "2026-04-27T23:58:40", "name": "xtensa: Apply further improvement to xtensa_legitimize_address()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501746/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229269/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229269/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=yahoo.co.jp header.i=@yahoo.co.jp header.a=rsa-sha256\n header.s=yahoocojp-202506 header.b=iPUsZw2B;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1777334320;\n s=yahoocojp-202506; d=yahoo.co.jp;\n h=References:Content-Transfer-Encoding:Content-Type:Subject:From:Cc:To:MIME-Version:Date:Message-ID;\n bh=NPOZbFf5Bb1rOmWfzj0ghilVn9EDtWPE+6mBFO580/4=;\n b=iPUsZw2BvTfH+LROYBhtxSTIH17vo7bIMP0zQ4Z5ULo8WxNhGzMuORR1vTNOZdn8\n A7degjjJUtWanm055T10JNtwPLAwO/8XX44gEEIEyNMBfiegHFnSzhH1PX0tiJx+0my\n Hfvk6Q5zxaV331QMrhQ/Z0Recv7C/PkJok9OQ2ujszq8e8nTI1uFNmOofi7Z3cNOuEY\n baCb17zN+F0IU9+iehdxqerMpozvxgnZTplSEcA8LmgCmUCnGkBQT9LBqk6phKLytYZ\n RFfLe9Pw24vFVAJ5Y1fYOthHT33Tx8fmcmEJKgA7riIlHed5Tm8aYs1zRwbPOyKYABh\n U4G0UlBI0Q==", "Message-ID": "<e179a50b-7829-49ec-84fe-e342bc37100a@yahoo.co.jp>", "Date": "Tue, 28 Apr 2026 08:58:40 +0900", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "gcc-patches@gcc.gnu.org", "Cc": "Max Filippov <jcmvbkbc@gmail.com>", "From": "Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>", "Subject": "[PATCH] xtensa: Apply further improvement to\n xtensa_legitimize_address()", "Content-Type": "text/plain; charset=UTF-8; format=flowed", "Content-Transfer-Encoding": "7bit", "References": "<e179a50b-7829-49ec-84fe-e342bc37100a.ref@yahoo.co.jp>", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "The load/store instructions in the Xtensa ISA have an unsigned 8-bit\ndisplacement immediate field that scales with the byte width of the\nreference. That is, for a 1-byte reference, the displacement is between\n0 and 255, for 2-bytes between 0 and 510, and for 4-bytes between 0 and\n1020.\n\nHowever, xtensa_legitimize_address() has not been able to take advantage\nof this fact until now, and has limited the maximum displacement to 255\nregardless of the reference byte width.\n\nThis patch resolves the above limitation and slightly improves the effi-\nciency of large positive displacements during memory accesses wider than\n1-byte.\n\n /* example */\n float test(float a[]) {\n return a[1] + a[8383] * a[16511];\n }\n\n ;; before (-O2)\n \t.literal_position\n \t.literal .LC0, 66044\n test:\n \tentry\tsp, 32\n \tl32r\ta8, .LC0\n \taddmi\ta9, a2, 0x300\n \tadd.n\ta8, a2, a8\n \taddmi\ta9, a9, 0x7f00\n \tlsi\tf0, a2, 4\n \tlsi\tf2, a9, 252\t;; 8383 = (32512 + 768 + 252) / 4\n \tlsi\tf1, a8, 0\t;; 16551 = 66044 / 4\n \tmadd.s\tf0, f2, f1\n \trfr\ta2, f0\n \tretw.n\n\n ;; after (-O2)\n test:\n \tentry\tsp, 32\n \taddmi\ta8, a2, 0x7f00\t;; CSEd\n \taddmi\ta9, a8, 0x7f00\n \tlsi\tf0, a2, 4\n \tlsi\tf2, a8, 1020\t;; 8383 = (32512 + 1020) / 4\n \tlsi\tf1, a9, 1020\t;; 16551 = (32512 + 32512 + 1020) / 4\n \tmadd.s\tf0, f2, f1\n \trfr\ta2, f0\n \tretw.n\n\ngcc/ChangeLog:\n\n\t* config/xtensa/xtensa.cc (xtensa_legitimize_address):\n\tModify to extend the upper limit of the coverable offset if the\n\taddress displacement of the corresponding machine instruction is\n\tgreater than 255.\n---\n gcc/config/xtensa/xtensa.cc | 68 +++++++++++++++++++++++--------------\n 1 file changed, 43 insertions(+), 25 deletions(-)", "diff": "diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc\nindex 0dc878086a5..39acdfea3ca 100644\n--- a/gcc/config/xtensa/xtensa.cc\n+++ b/gcc/config/xtensa/xtensa.cc\n@@ -2314,7 +2314,8 @@ xtensa_legitimize_address (rtx x,\n \t\t\t machine_mode mode)\n {\n rtx plus0, plus1, temp;\n- HOST_WIDE_INT offset, mem_offset, addmi_offset;\n+ HOST_WIDE_INT offset, mem_disp, delta, offset2;\n+ int mode_size;\n \n if (xtensa_tls_symbol_p (x))\n return xtensa_legitimize_tls_address (x);\n@@ -2326,33 +2327,50 @@ xtensa_legitimize_address (rtx x,\n if (! REG_P (plus0) && REG_P (plus1))\n std::swap (plus0, plus1);\n \n- /* Try to split up the offset to use up to two ADDMI instructions. */\n- if (REG_P (plus0) && CONST_INT_P (plus1)\n- && ! xtensa_mem_offset (offset = INTVAL (plus1), mode)\n- && ! xtensa_simm8 (offset)\n- && xtensa_mem_offset (mem_offset = offset & 0xff, mode))\n+ /* Try to split up the offset to use up to two ADDMI instructions;\n+ The two ADDMIs are slightly more efficient than \"L32R w/litpool + ADD\"\n+ or \"CONST16 pair + ADD\", if applicable. */\n+ if (! REG_P (plus0) || ! CONST_INT_P (plus1)\n+ || xtensa_mem_offset (offset = INTVAL (plus1), mode)\n+ || xtensa_simm8 (offset)\n+ || ! xtensa_mem_offset (mem_disp = offset & 0xff, mode))\n+ return x;\n+\n+ /* The above assumes that the displacement within the load/store instruc-\n+ tion is unsigned 8 bits, regardless of the load/store width. However,\n+ in actual 2- or 4-byte width load/store instructions, a displacement\n+ shifted by 1 or 2 bits, respectively, is added to the base register.\n+ Here, determine the amount of displacement delta that these instructions\n+ can cover extra range. */\n+ if ((mode_size = GET_MODE_SIZE (mode)) == 2)\n+ delta = 256;\n+ else if (mode_size >= 4)\n+ delta = 768;\n+ else\n+ delta = 0;\n+\n+ /* The upper limit of the ADDMI instruction's addition is allowed to be\n+ widened by the delta amount calculated above, and the excess is later\n+ renormalized to the displacement of the load/store instrution. */\n+ offset2 = offset & ~0xff, offset = 0;\n+ if (! IN_RANGE (offset2, -32768, 32512 + delta))\n {\n- /* The two ADDMIs are slightly more efficient than\n-\t \"L32R w/litpool + ADD\" or \"CONST16 pair + ADD\", if applicable. */\n- addmi_offset = offset & ~0xff;\n- if (addmi_offset > 32512)\n-\toffset = 32512, addmi_offset -= 32512;\n- else if (addmi_offset < -32768)\n-\toffset = -32768, addmi_offset += 32768;\n- else\n-\toffset = 0;\n+ if (offset2 > 32512)\n+\toffset = 32512, offset2 -= 32512;\n+ else if (offset2 < -32768)\n+\toffset = -32768, offset2 += 32768;\n \n- if (xtensa_simm8x256 (addmi_offset))\n-\t{\n-\t emit_insn (gen_addsi3 (temp = gen_reg_rtx (Pmode),\n-\t\t\t\t plus0, GEN_INT (addmi_offset)));\n-\t if (offset)\n-\t emit_insn (gen_addsi3 (temp, temp, GEN_INT (offset)));\n-\t return gen_rtx_PLUS (Pmode, temp, GEN_INT (mem_offset));\n-\t}\n+ if (! IN_RANGE (offset2, -32768, 32512 + delta))\n+\treturn x;\n }\n-\n- return x;\n+ if (offset2 > 32512)\n+ mem_disp += offset2 - 32512, offset2 = 32512;\n+\n+ emit_insn (gen_addsi3 (temp = gen_reg_rtx (Pmode),\n+\t\t\t plus0, GEN_INT (offset2)));\n+ if (offset)\n+ emit_insn (gen_addsi3 (temp, temp, GEN_INT (offset)));\n+ return gen_rtx_PLUS (Pmode, temp, GEN_INT (mem_disp));\n }\n \n /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.\n", "prefixes": [] }