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GET /api/1.1/patches/2229251/?format=api
{ "id": 2229251, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229251/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260427221155.2144848-25-dakr@kernel.org/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427221155.2144848-25-dakr@kernel.org>", "date": "2026-04-27T22:11:22", "name": "[REF,24/24] gpu: drm: tyr: use HRT lifetime for IoMem", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "0edba699d929e9238d13f046964ce4fdb14fbc58", "submitter": { "id": 89037, "url": "http://patchwork.ozlabs.org/api/1.1/people/89037/?format=api", "name": "Danilo Krummrich", "email": "dakr@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260427221155.2144848-25-dakr@kernel.org/mbox/", "series": [ { "id": 501734, "url": "http://patchwork.ozlabs.org/api/1.1/series/501734/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=501734", "date": "2026-04-27T22:10:58", "name": "rust: device: Higher-Ranked Lifetime Types for device drivers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501734/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229251/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229251/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pwm+bounces-8727-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org 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(conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 00944301151A\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:15:51 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 5C7CA3B27F4;\n\tMon, 27 Apr 2026 22:14:40 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 376BD3ACA51;\n\tMon, 27 Apr 2026 22:14:39 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id DB888C2BCB5;\n\tMon, 27 Apr 2026 22:14:33 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777328080; cv=none;\n b=ZkkbS2KDorAtzqLFmTeutEzLbFAEEmz+xrnmddOMMY7pyc7dJIfcEZ1aKKeISH1vGEipMB3z9OiLGpShe8iibtEYg4NQeFNuan3DCJBrPFhVMn2338Gn//Hi66A0XBysRKyghAiNgLfXoYOoI1O9xHmvpciXSEWVZmoQjGSMT1c=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777328080; c=relaxed/simple;\n\tbh=E8DtrBLrYNArPpJF86GXwFeCoMuUblCF+p22mHtKF5E=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=jVsa/qO2UFvOfc3qJgrxJFAIB46zgcorZu2VqrKD1D72v2vMcWUfn6LmJQO5PdKgCjYpYqT87cLeGTo8Tbn3RMeLloQj6Om3tDL9L6vvFM63ch2T1ejFOJZvw3oJbsVAcGuwAoh7HHExRIi9NPNOdkjGmsrozpQ3Q/1NyJPRmQA=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=p6W4oeKO; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777328079;\n\tbh=E8DtrBLrYNArPpJF86GXwFeCoMuUblCF+p22mHtKF5E=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=p6W4oeKOQM7jk9jUoesyFgPltNs3rvUvJ9lYlQcxOYgJ6MKYpnV/2PWjGc4O6Z2eb\n\t OR2tKoInE0qj80ZUwdAGFDLG4KTetFGk1Mcf4t5ByMJsB3c1ULTqJ3Usu1SZh1w1TO\n\t WxDVArGn6/bxZq0SsSxaYf6HzaY4TXNrLwAMm4lr3cW8GW/thYh6Nz8M8ORmihfJr9\n\t OqI6G35dQV1DQq9pVVfRW9IxKUFn7KltdTAEQagbAfhmotKOyNua/Lke93ARGdheGU\n\t dC3a4xk7VM5u4w1NFuaIIZSl2DV6pVKkWCaY0owAM0qH7kTKDX66LvYg4HueAW+yn+\n\t bT5jiQBXLlbsA==", "From": "Danilo Krummrich <dakr@kernel.org>", "To": "gregkh@linuxfoundation.org,\n\trafael@kernel.org,\n\tacourbot@nvidia.com,\n\taliceryhl@google.com,\n\tdavid.m.ertman@intel.com,\n\tira.weiny@intel.com,\n\tleon@kernel.org,\n\tviresh.kumar@linaro.org,\n\tm.wilczynski@samsung.com,\n\tukleinek@kernel.org,\n\tbhelgaas@google.com,\n\tkwilczynski@kernel.org,\n\tabdiel.janulgue@gmail.com,\n\trobin.murphy@arm.com,\n\tmarkus.probst@posteo.de,\n\tojeda@kernel.org,\n\tboqun@kernel.org,\n\tgary@garyguo.net,\n\tbjorn3_gh@protonmail.com,\n\tlossin@kernel.org,\n\ta.hindborg@kernel.org,\n\ttmgross@umich.edu", "Cc": "driver-core@lists.linux.dev,\n\tlinux-kernel@vger.kernel.org,\n\tnova-gpu@lists.linux.dev,\n\tdri-devel@lists.freedesktop.org,\n\tlinux-pm@vger.kernel.org,\n\tlinux-pwm@vger.kernel.org,\n\tlinux-pci@vger.kernel.org,\n\trust-for-linux@vger.kernel.org,\n\tDanilo Krummrich <dakr@kernel.org>", "Subject": "[PATCH REF 24/24] gpu: drm: tyr: use HRT lifetime for IoMem", "Date": "Tue, 28 Apr 2026 00:11:22 +0200", "Message-ID": "<20260427221155.2144848-25-dakr@kernel.org>", "X-Mailer": "git-send-email 2.54.0", "In-Reply-To": "<20260427221155.2144848-1-dakr@kernel.org>", "References": "<20260427221155.2144848-1-dakr@kernel.org>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Take advantage of the lifetime-parameterized IoMem<'a> to use the\nmemory mapping directly during probe, eliminating the Arc<Devres<IoMem>>\nindirection.\n\nSince the IoMem is only used during probe, this also simplifies\nRegister::read/write to be infallible -- the Devres access check is no\nlonger needed, so reads return u32 directly and writes return ().\n\nSigned-off-by: Danilo Krummrich <dakr@kernel.org>\n---\nNot yet updated to Tyr using the register!() macro, but probably good enough for\nreference.\n---\n drivers/gpu/drm/tyr/driver.rs | 14 ++++----\n drivers/gpu/drm/tyr/gpu.rs | 62 +++++++++++++++++------------------\n drivers/gpu/drm/tyr/regs.rs | 21 +++---------\n 3 files changed, 41 insertions(+), 56 deletions(-)", "diff": "diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs\nindex eaa84efdfdf7..d305ad433e03 100644\n--- a/drivers/gpu/drm/tyr/driver.rs\n+++ b/drivers/gpu/drm/tyr/driver.rs\n@@ -10,7 +10,6 @@\n Core,\n Device, //\n },\n- devres::Devres,\n drm,\n drm::ioctl,\n io::poll,\n@@ -23,7 +22,6 @@\n sizes::SZ_2M,\n sync::{\n aref::ARef,\n- Arc,\n Mutex, //\n },\n time, //\n@@ -37,7 +35,7 @@\n regs, //\n };\n \n-pub(crate) type IoMem = kernel::io::mem::IoMem<'static, SZ_2M>;\n+pub(crate) type IoMem = kernel::io::Mmio<SZ_2M>;\n \n pub(crate) struct TyrDrmDriver;\n \n@@ -65,11 +63,11 @@ pub(crate) struct TyrDrmDeviceData {\n pub(crate) gpu_info: GpuInfo,\n }\n \n-fn issue_soft_reset(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result {\n- regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?;\n+fn issue_soft_reset(dev: &Device<Bound>, iomem: &IoMem) -> Result {\n+ regs::GPU_CMD.write(iomem, regs::GPU_CMD_SOFT_RESET);\n \n poll::read_poll_timeout(\n- || regs::GPU_IRQ_RAWSTAT.read(dev, iomem),\n+ || Ok(regs::GPU_IRQ_RAWSTAT.read(iomem)),\n |status| *status & regs::GPU_IRQ_RAWSTAT_RESET_COMPLETED != 0,\n time::Delta::from_millis(1),\n time::Delta::from_millis(100),\n@@ -109,12 +107,12 @@ fn probe(\n let sram_regulator = Regulator::<regulator::Enabled>::get(pdev.as_ref(), c\"sram\")?;\n \n let request = pdev.io_request_by_index(0).ok_or(ENODEV)?;\n- let iomem = Arc::new(request.iomap_sized::<SZ_2M>()?.into_devres()?, GFP_KERNEL)?;\n+ let iomem = request.iomap_sized::<SZ_2M>()?;\n \n issue_soft_reset(pdev.as_ref(), &iomem)?;\n gpu::l2_power_on(pdev.as_ref(), &iomem)?;\n \n- let gpu_info = GpuInfo::new(pdev.as_ref(), &iomem)?;\n+ let gpu_info = GpuInfo::new(&iomem);\n gpu_info.log(pdev);\n \n let platform: ARef<platform::Device> = pdev.into();\ndiff --git a/drivers/gpu/drm/tyr/gpu.rs b/drivers/gpu/drm/tyr/gpu.rs\nindex a88775160f98..bb0473c85bf7 100644\n--- a/drivers/gpu/drm/tyr/gpu.rs\n+++ b/drivers/gpu/drm/tyr/gpu.rs\n@@ -10,7 +10,6 @@\n Bound,\n Device, //\n },\n- devres::Devres,\n io::poll,\n platform,\n prelude::*,\n@@ -35,37 +34,36 @@\n pub(crate) struct GpuInfo(pub(crate) uapi::drm_panthor_gpu_info);\n \n impl GpuInfo {\n- pub(crate) fn new(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<Self> {\n- let gpu_id = regs::GPU_ID.read(dev, iomem)?;\n- let csf_id = regs::GPU_CSF_ID.read(dev, iomem)?;\n- let gpu_rev = regs::GPU_REVID.read(dev, iomem)?;\n- let core_features = regs::GPU_CORE_FEATURES.read(dev, iomem)?;\n- let l2_features = regs::GPU_L2_FEATURES.read(dev, iomem)?;\n- let tiler_features = regs::GPU_TILER_FEATURES.read(dev, iomem)?;\n- let mem_features = regs::GPU_MEM_FEATURES.read(dev, iomem)?;\n- let mmu_features = regs::GPU_MMU_FEATURES.read(dev, iomem)?;\n- let thread_features = regs::GPU_THREAD_FEATURES.read(dev, iomem)?;\n- let max_threads = regs::GPU_THREAD_MAX_THREADS.read(dev, iomem)?;\n- let thread_max_workgroup_size = regs::GPU_THREAD_MAX_WORKGROUP_SIZE.read(dev, iomem)?;\n- let thread_max_barrier_size = regs::GPU_THREAD_MAX_BARRIER_SIZE.read(dev, iomem)?;\n- let coherency_features = regs::GPU_COHERENCY_FEATURES.read(dev, iomem)?;\n-\n- let texture_features = regs::GPU_TEXTURE_FEATURES0.read(dev, iomem)?;\n-\n- let as_present = regs::GPU_AS_PRESENT.read(dev, iomem)?;\n-\n- let shader_present = u64::from(regs::GPU_SHADER_PRESENT_LO.read(dev, iomem)?);\n+ pub(crate) fn new(iomem: &IoMem) -> Self {\n+ let gpu_id = regs::GPU_ID.read(iomem);\n+ let csf_id = regs::GPU_CSF_ID.read(iomem);\n+ let gpu_rev = regs::GPU_REVID.read(iomem);\n+ let core_features = regs::GPU_CORE_FEATURES.read(iomem);\n+ let l2_features = regs::GPU_L2_FEATURES.read(iomem);\n+ let tiler_features = regs::GPU_TILER_FEATURES.read(iomem);\n+ let mem_features = regs::GPU_MEM_FEATURES.read(iomem);\n+ let mmu_features = regs::GPU_MMU_FEATURES.read(iomem);\n+ let thread_features = regs::GPU_THREAD_FEATURES.read(iomem);\n+ let max_threads = regs::GPU_THREAD_MAX_THREADS.read(iomem);\n+ let thread_max_workgroup_size = regs::GPU_THREAD_MAX_WORKGROUP_SIZE.read(iomem);\n+ let thread_max_barrier_size = regs::GPU_THREAD_MAX_BARRIER_SIZE.read(iomem);\n+ let coherency_features = regs::GPU_COHERENCY_FEATURES.read(iomem);\n+\n+ let texture_features = regs::GPU_TEXTURE_FEATURES0.read(iomem);\n+\n+ let as_present = regs::GPU_AS_PRESENT.read(iomem);\n+\n+ let shader_present = u64::from(regs::GPU_SHADER_PRESENT_LO.read(iomem));\n let shader_present =\n- shader_present | u64::from(regs::GPU_SHADER_PRESENT_HI.read(dev, iomem)?) << 32;\n+ shader_present | u64::from(regs::GPU_SHADER_PRESENT_HI.read(iomem)) << 32;\n \n- let tiler_present = u64::from(regs::GPU_TILER_PRESENT_LO.read(dev, iomem)?);\n- let tiler_present =\n- tiler_present | u64::from(regs::GPU_TILER_PRESENT_HI.read(dev, iomem)?) << 32;\n+ let tiler_present = u64::from(regs::GPU_TILER_PRESENT_LO.read(iomem));\n+ let tiler_present = tiler_present | u64::from(regs::GPU_TILER_PRESENT_HI.read(iomem)) << 32;\n \n- let l2_present = u64::from(regs::GPU_L2_PRESENT_LO.read(dev, iomem)?);\n- let l2_present = l2_present | u64::from(regs::GPU_L2_PRESENT_HI.read(dev, iomem)?) << 32;\n+ let l2_present = u64::from(regs::GPU_L2_PRESENT_LO.read(iomem));\n+ let l2_present = l2_present | u64::from(regs::GPU_L2_PRESENT_HI.read(iomem)) << 32;\n \n- Ok(Self(uapi::drm_panthor_gpu_info {\n+ Self(uapi::drm_panthor_gpu_info {\n gpu_id,\n gpu_rev,\n csf_id,\n@@ -88,7 +86,7 @@ pub(crate) fn new(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<Self> {\n core_features,\n pad: 0,\n gpu_features: 0,\n- }))\n+ })\n }\n \n pub(crate) fn log(&self, pdev: &platform::Device) {\n@@ -208,11 +206,11 @@ fn from(value: u32) -> Self {\n }\n \n /// Powers on the l2 block.\n-pub(crate) fn l2_power_on(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result {\n- regs::L2_PWRON_LO.write(dev, iomem, 1)?;\n+pub(crate) fn l2_power_on(dev: &Device<Bound>, iomem: &IoMem) -> Result {\n+ regs::L2_PWRON_LO.write(iomem, 1);\n \n poll::read_poll_timeout(\n- || regs::L2_READY_LO.read(dev, iomem),\n+ || Ok(regs::L2_READY_LO.read(iomem)),\n |status| *status == 1,\n Delta::from_millis(1),\n Delta::from_millis(100),\ndiff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs\nindex 611870c2e6af..0881b3812afd 100644\n--- a/drivers/gpu/drm/tyr/regs.rs\n+++ b/drivers/gpu/drm/tyr/regs.rs\n@@ -7,16 +7,7 @@\n // does.\n #![allow(dead_code)]\n \n-use kernel::{\n- bits::bit_u32,\n- device::{\n- Bound,\n- Device, //\n- },\n- devres::Devres,\n- io::Io,\n- prelude::*, //\n-};\n+use kernel::{bits::bit_u32, io::Io};\n \n use crate::driver::IoMem;\n \n@@ -29,15 +20,13 @@\n \n impl<const OFFSET: usize> Register<OFFSET> {\n #[inline]\n- pub(crate) fn read(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<u32> {\n- let value = (*iomem).access(dev)?.read32(OFFSET);\n- Ok(value)\n+ pub(crate) fn read(&self, iomem: &IoMem) -> u32 {\n+ iomem.read32(OFFSET)\n }\n \n #[inline]\n- pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u32) -> Result {\n- (*iomem).access(dev)?.write32(value, OFFSET);\n- Ok(())\n+ pub(crate) fn write(&self, iomem: &IoMem, value: u32) {\n+ iomem.write32(value, OFFSET);\n }\n }\n \n", "prefixes": [ "REF", "24/24" ] }