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GET /api/1.1/patches/2229203/?format=api
{ "id": 2229203, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229203/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/cc1d9fdb-f46c-4610-b82b-f0b218656d3f@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<cc1d9fdb-f46c-4610-b82b-f0b218656d3f@oss.qualcomm.com>", "date": "2026-04-27T22:07:55", "name": "[V2,to-be-committed,RISC-V,PR,tree-optimization/57650] Detect more czero opportunities", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "12bae353399f2eb008a141c9b1e205022aaedd29", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/cc1d9fdb-f46c-4610-b82b-f0b218656d3f@oss.qualcomm.com/mbox/", "series": [ { "id": 501732, "url": "http://patchwork.ozlabs.org/api/1.1/series/501732/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501732", "date": "2026-04-27T22:07:55", "name": "[V2,to-be-committed,RISC-V,PR,tree-optimization/57650] Detect more czero opportunities", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501732/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229203/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229203/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=CT0wyLhA;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=iRdq8OiS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------WMApEN1SFWhiEnaNIBooP3EN\"", "Message-ID": "<cc1d9fdb-f46c-4610-b82b-f0b218656d3f@oss.qualcomm.com>", "Date": "Mon, 27 Apr 2026 16:07:55 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "Subject": "[V2][to-be-committed][RISC-V][PR tree-optimization/57650] Detect more\n czero opportunities", "X-Proofpoint-GUID": "zH6PqDu1XfWhnOYkvX4MpFb_Y7yoq0yi", "X-Authority-Analysis": "v=2.4 cv=PcrPQChd c=1 sm=1 tr=0 ts=69efde3f cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=iT5GfrjKS2Jy2cOH28cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=vMX7aGxdZBRmIcbt_ogA:9 a=B2y7HmGcmWMA:10 a=scEy_gLbYbu1JhEsrz4S:22", "X-Proofpoint-ORIG-GUID": "zH6PqDu1XfWhnOYkvX4MpFb_Y7yoq0yi", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI3MDIzNCBTYWx0ZWRfX06SXah1hSHq8\n jZzQud2Xenketz+dQ3nXQUUHCgK4lm9pE9TlMpJ4PT+uDjeMKYpokoFKfT82Yo2B56lD6ivFxg9\n jfrW4sLwC7NnUlNSDm91olVnfJ9TB6mVIzSI3BHKz/UQnt17kkMq3xcevqISIah1LMY6WCCJzlO\n xC0Efad9j66D9IOZf8nOagAvgrCx7vYMR3O0kHwq/82NwQLMFYG2uS9SUZvUCbjYqczkdoe1/KG\n 7FA+m00ZKqAWx24ZUWKNnpAhK6XBiM1CRE7ILgH8p+WHreTR+Zb65nI9f0GHPmpsJmyIz94GMjf\n Kfb/YbZ0GRETKEwkkOPAzR9YtFmUH7aJfwx6gYCZRCoGzSbqLzANCESBVUlJoa21+eot6symWjP\n /Zzm9wr9v5eIZZImhJiniolI2i3tl2HtE4tPKfIn4nbJH3BaLJ4N6W0p4rM7M2r43OckenK0vKo\n CrS8EnRHGJHU90GIkaQ==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-27_04,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015\n malwarescore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270234", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "So the pre-commit CI system was failing with the original patch. This \nwas ultimately tracked down to the RISC-V pre-commit system specifying a \ntuning flag (!?!). So rather than the generic tuning with a branch cost \nof 4, we got rocket tuning witha branch cost of 3. That in turn caused \nthe if-converter to fail to convert a conditional branch in the expected \nway.\n\nSo the V2 patch just forces -mbranch-cost=4 since that's really the key \ntuning flag to get right. I'm going to push this since the compiler \nchanges have already been correctness tested and it's just the tuning \nadjustment in the testsuite to make it happy.\n\nJeff\ncommit a80a8b2533c22a698f21d1ec8f5e5cbe3918671c\nAuthor: Jeff Law <jeffrey.law@oss.qualcomm.com>\nDate: Mon Apr 27 16:03:53 2026 -0600\n\n [RISC-V][PR tree-optimization/57650] Detect more czero opportunities\n \n So in pr57650 we have RTL like this:\n \n > (set (reg:DI 147)\n > (and:DI (gt:DI (reg:DI 153 [ y ])\n > (reg:DI 154 [ z ]))\n > (ne:DI (reg/v/f:DI 138 [ x ])\n > (const_int 0 [0]))))\n \n That's going to generate:\n \n sgt a1,a1,a2\n snez a5,a0\n and a5,a5,a1\n \n But with zicond we can do better. That's really just:\n \n sgt a1,a1,a2\n czero.eqz a1,a1,a0\n \n We already had patterns to clean this kind of mess up a bit, but they needed a\n bit more generalization. First they only accepted NE forms, but EQ is just as\n valid and just requires us to select between czero.nez and czero.eqz. Second\n the AND is commutative, so the equality test can appear in either position.\n With those generalizations we can get the desired code. Note I'm not trying to\n tackle the larger problems with 57650, just the low level code generation\n inefficiencies.\n \n This has been in my tester for a while without regressions and is being\n exercised during a bootstrap on the BPI. I'll wait for pre-commit CI to render\n a verdict.\n \n PR tree-optimization/57650\n gcc/\n * config/riscv/zicond.md: Generalize patterns which identify\n a logical AND of an equality test and some other sCC insn to\n handle more cases.\n \n gcc/testsuite/\n * gcc.target/riscv/pr57650.c: New test.", "diff": "diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md\nindex 2aefcff4fef..ac1aa3a6b7e 100644\n--- a/gcc/config/riscv/zicond.md\n+++ b/gcc/config/riscv/zicond.md\n@@ -128,111 +128,101 @@ (define_split\n ;; In some cases gimple can give us a sequence with a logical and\n ;; of two sCC insns. This can be implemented an sCC feeding a\n ;; conditional zero.\n+;;\n+;; AND is commutative, so every form has two variants\n (define_split\n [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (ne:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (scc_0:X (match_operand:X 2 \"register_operand\")\n-\t\t\t(match_operand:X 3 \"reg_or_0_operand\"))))\n- (clobber (match_operand:X 4 \"register_operand\"))]\n+\t(and:X (match_operator:X 1 \"equality_operator\"\n+\t\t[(match_operand:X 2 \"register_operand\") (const_int 0)])\n+\t (scc_0:X (match_operand:X 3 \"register_operand\")\n+\t\t\t(match_operand:X 4 \"reg_or_0_operand\"))))\n+ (clobber (match_operand:X 5 \"register_operand\"))]\n \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 4) (scc_0:X (match_dup 2) (match_dup 3)))\n- (set (match_dup 0) (if_then_else:X (eq:X (match_dup 1) (const_int 0))\n+ [(set (match_dup 5) (scc_0:X (match_dup 3) (match_dup 4)))\n+ (set (match_dup 0) (if_then_else:X (match_op_dup 1\n+\t\t\t\t\t[(match_dup 2) (const_int 0)])\n \t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 4)))])\n+\t\t\t\t (match_dup 5)))]\n+ { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })\n \n-;; Similarly but GE/GEU which requires (const_int 1) as an operand.\n (define_split\n [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (ne:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (any_ge:X (match_operand:X 2 \"register_operand\")\n-\t\t\t (const_int 1))))\n- (clobber (match_operand:X 3 \"register_operand\"))]\n+\t(and:X (scc_0:X (match_operand:X 3 \"register_operand\")\n+\t\t\t(match_operand:X 4 \"reg_or_0_operand\"))\n+\t (match_operator:X 1 \"equality_operator\"\n+\t\t[(match_operand:X 2 \"register_operand\") (const_int 0)])))\n+ (clobber (match_operand:X 5 \"register_operand\"))]\n \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 3) (any_ge:X (match_dup 2) (const_int 1)))\n- (set (match_dup 0) (if_then_else:X (eq:X (match_dup 1) (const_int 0))\n+ [(set (match_dup 5) (scc_0:X (match_dup 3) (match_dup 4)))\n+ (set (match_dup 0) (if_then_else:X (match_op_dup:X 1\n+\t\t\t\t\t[(match_dup 2) (const_int 0)])\n \t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 3)))])\n+\t\t\t\t (match_dup 5)))]\n+ { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })\n \n-;; Similarly but LU/LTU which allows an arith_operand\n-(define_split\n- [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (ne:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (any_lt:X (match_operand:X 2 \"register_operand\")\n-\t\t\t (match_operand:X 3 \"arith_operand\"))))\n- (clobber (match_operand:X 4 \"register_operand\"))]\n- \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 4) (any_lt:X (match_dup 2) (match_dup 3)))\n- (set (match_dup 0) (if_then_else:X (eq:X (match_dup 1) (const_int 0))\n-\t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 4)))])\n \n-;; Finally LE/LEU which requires sle_operand.\n+;; Similarly but GE/GEU which requires (const_int 1) as an operand.\n (define_split\n [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (ne:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (any_le:X (match_operand:X 2 \"register_operand\")\n-\t\t\t (match_operand:X 3 \"sle_operand\"))))\n+\t(and:X (match_operator:X 1 \"equality_operator\"\n+\t\t[(match_operand:X 2 \"register_operand\") (const_int 0)])\n+\t (any_ge:X (match_operand:X 3 \"register_operand\")\n+\t\t\t (const_int 1))))\n (clobber (match_operand:X 4 \"register_operand\"))]\n \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 4) (any_le:X (match_dup 2) (match_dup 3)))\n- (set (match_dup 0) (if_then_else:X (eq:X (match_dup 1) (const_int 0))\n+ [(set (match_dup 4) (any_ge:X (match_dup 3) (const_int 1)))\n+ (set (match_dup 0) (if_then_else:X (match_op_dup:X 1\n+\t\t\t\t [(match_dup 2) (const_int 0)])\n \t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 4)))])\n-\n+\t\t\t\t (match_dup 4)))]\n+ { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })\n \n-;; Inverted versions from above. I tried to get this to work with\n-;; iterators, but didn't have any success disambiguating the code attr\n-;; for the eq/ne flip we have to do.\n (define_split\n [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (eq:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (scc_0:X (match_operand:X 2 \"register_operand\")\n-\t\t\t(match_operand:X 3 \"reg_or_0_operand\"))))\n+\t(and:X (any_ge:X (match_operand:X 3 \"register_operand\")\n+\t\t\t (const_int 1))\n+\t (match_operator:X 1 \"equality_operator\"\n+\t\t[(match_operand:X 2 \"register_operand\") (const_int 0)])))\n (clobber (match_operand:X 4 \"register_operand\"))]\n \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 4) (scc_0:X (match_dup 2) (match_dup 3)))\n- (set (match_dup 0) (if_then_else:X (ne:X (match_dup 1) (const_int 0))\n-\t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 4)))])\n-\n-;; Similarly but GE/GEU which requires (const_int 1) as an operand.\n-(define_split\n- [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (eq:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (any_ge:X (match_operand:X 2 \"register_operand\")\n-\t\t\t (const_int 1))))\n- (clobber (match_operand:X 3 \"register_operand\"))]\n- \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 3) (any_ge:X (match_dup 2) (const_int 1)))\n- (set (match_dup 0) (if_then_else:X (ne:X (match_dup 1) (const_int 0))\n+ [(set (match_dup 4) (any_ge:X (match_dup 3) (const_int 1)))\n+ (set (match_dup 0) (if_then_else:X (match_op_dup:X 1\n+\t\t\t\t [(match_dup 2) (const_int 0)])\n \t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 3)))])\n+\t\t\t\t (match_dup 4)))]\n+ { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })\n \n ;; Similarly but LU/LTU which allows an arith_operand\n (define_split\n [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (eq:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (any_lt:X (match_operand:X 2 \"register_operand\")\n-\t\t\t (match_operand:X 3 \"arith_operand\"))))\n- (clobber (match_operand:X 4 \"register_operand\"))]\n+\t(and:X (match_operator:X 1 \"equality_operator\"\n+\t\t[(match_operand:X 2 \"register_operand\") (const_int 0)])\n+\t (any_lt:X (match_operand:X 3 \"register_operand\")\n+\t\t\t (match_operand:X 4 \"arith_operand\"))))\n+ (clobber (match_operand:X 5 \"register_operand\"))]\n \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 4) (any_lt:X (match_dup 2) (match_dup 3)))\n- (set (match_dup 0) (if_then_else:X (ne:X (match_dup 1) (const_int 0))\n+ [(set (match_dup 5) (any_lt:X (match_dup 3) (match_dup 4)))\n+ (set (match_dup 0) (if_then_else:X (match_op_dup:X 1\n+\t\t\t\t [(match_dup 2) (const_int 0)])\n \t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 4)))])\n+\t\t\t\t (match_dup 5)))]\n+ { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })\n \n ;; Finally LE/LEU which requires sle_operand.\n (define_split\n [(set (match_operand:X 0 \"register_operand\")\n-\t(and:X (eq:X (match_operand:X 1 \"register_operand\") (const_int 0))\n-\t (any_le:X (match_operand:X 2 \"register_operand\")\n-\t\t\t (match_operand:X 3 \"sle_operand\"))))\n- (clobber (match_operand:X 4 \"register_operand\"))]\n+\t(and:X (match_operator:X 1 \"equality_operator\"\n+\t\t[(match_operand:X 2 \"register_operand\") (const_int 0)])\n+\t (any_le:X (match_operand:X 3 \"register_operand\")\n+\t\t\t (match_operand:X 4 \"sle_operand\"))))\n+ (clobber (match_operand:X 5 \"register_operand\"))]\n \"TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV\"\n- [(set (match_dup 4) (any_le:X (match_dup 2) (match_dup 3)))\n- (set (match_dup 0) (if_then_else:X (ne:X (match_dup 1) (const_int 0))\n+ [(set (match_dup 5) (any_le:X (match_dup 3) (match_dup 4)))\n+ (set (match_dup 0) (if_then_else:X (match_op_dup:X 1\n+\t\t\t\t [(match_dup 2) (const_int 0)])\n \t\t\t\t (const_int 0)\n-\t\t\t\t (match_dup 4)))])\n+\t\t\t\t (match_dup 5)))]\n+ { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })\n \n ;; We can splat the sign bit across a GPR with a arithmetic right shift\n ;; which gives us a 0, -1 result. We then turn on bit #0 unconditionally\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr57650.c b/gcc/testsuite/gcc.target/riscv/pr57650.c\nnew file mode 100644\nindex 00000000000..d6da43ebe22\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr57650.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gc_zicond -mabi=ilp32 -mbranch-cost=4\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Os\" \"-Og\" \"-Oz\" } } */\n+\n+int baz (int);\n+\n+int\n+bar (char *x, int y, int z)\n+{\n+ if (x && y > z)\n+ return baz (1);\n+ return 0;\n+}\n+\n+/* { dg-final { scan-assembler-not \"snez\\t\" } } */\n+/* { dg-final { scan-assembler-not \"seq\\t\" } } */\n+/* { dg-final { scan-assembler-times \"czero\" 1 } } */\n", "prefixes": [ "V2", "to-be-committed", "RISC-V", "PR", "tree-optimization/57650" ] }