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GET /api/1.1/patches/2229157/?format=api
{ "id": 2229157, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229157/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-4-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-4-mhonap@nvidia.com>", "date": "2026-04-27T18:12:29", "name": "[RFC,3/9] linux-headers: Update vfio.h for CXL Type-2 device passthrough", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "160d18d3058dcad9601b0861d12e9238a1941d93", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-4-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229157/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229157/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=k+pyAjzL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c107::1;\n envelope-from=mhonap@nvidia.com;\n helo=PH8PR06CU001.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 3/9] linux-headers: Update vfio.h for CXL Type-2 device\n passthrough", "Date": "Mon, 27 Apr 2026 23:42:29 +0530", "Message-ID": "<20260427181235.3003865-4-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260427181235.3003865-1-mhonap@nvidia.com>", "References": "<20260427181235.3003865-1-mhonap@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FD:EE_|CH3PR12MB7547:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c91c68aa-cc24-44e3-5072-08dea488c56a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|36860700016|7416014|376014|1800799024|56012099003|22082099003|18002099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n NOirRJeu/eGYudNj1nciC3miNkxveyC/kzbA7mUla8C+PyYz3Yl8piMWRUJmzq6EB2JeDPQeK2UGoEAvWjQDi2HgVgE1BQb9MnbWPOiJ/GljAQs0gLAHLCtCHQPGDJgzswjr+T3S0oc2PHwJyzmTgYCbyIm89wrigzlh5RtZaOsVNADnmxjyIvQ0fxOYoxobQdtR/uv3pAi719GjovsWrjyX9QYABPrSEOM48ula4pnfthxhaQGtCge2532W+272jteWmSLzFmrTaL3yiExL3/eLm9f9kMyAoDyWAD5aMJpqhTcD6ZO0nghJfSkte+mnAtgNFe9yYHqphPSYC7ImanBlnt0MHCLUyb0hFk6XB0PO55+64QKKIlo/fqniOcwJiTecPnRZyv66j3COtmHwA1vO6omgBtKrSuLG/xwN6u45bP6X5UGYdfMqtlAcmh7vBnA9gpPJgNGrssMN8Mpg0jNJ2V60RrjMYqZZAD43cxYM/h5IcikYBNvn7LkADLjrmEoaEViphMIRthbkpRVjRWeILSzDC1uyFqTnbTmx9fAGs4PqdNN3BH6//s5+tfZhZWhp9WlorfQsDE399mLfo3aJ3MOtcSsFOWu6uAr71OpDjlmp0U5V00N0y8hXmlKDDlxqgAuo15z6mcw5ElsGFcxjmU+OiNkyk9i7eS/M7n4T1BLTqyw1OOjlaasB4/Qa+PeKb2qebfETuI7GTLdqguEmG72aftygUJwkn4c4Ovz1Vpa8A4BYda7ffyLfReFMPJjGAqRSg/0WKGbSZEkugPqpBXsBlaMfDs3HdXwCjYzhZGlgMe3VxpFvi+1RYL9L", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FD.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB7547", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nSync the VFIO UAPI additions from the kernel CXL Type-2 passthrough\nseries.\n\nVFIO_DEVICE_FLAGS_CXL (bit 9) marks a device as CXL Type-2 and\nguarantees the capability chain includes a vfio_device_info_cap_cxl\nentry (cap id 6). That capability carries the BAR index holding the\nCXL component registers, flags for firmware-committed and cache-capable\ndevices, the byte offset to the HDM Decoder Capability block within\nthat BAR, and region indices for both the DPA memory region and the\nComponent Register shadow.\n\nTwo new region subtypes:\n VFIO_REGION_SUBTYPE_CXL (1): mmappable DPA memory\n VFIO_REGION_SUBTYPE_CXL_COMP_REGS (2): HDM decoder shadow, r/w only\n\nNote: UAPI headers are normally kept in sync via\nscripts/update-linux-headers.sh once upstream kernel changes merge.\nThis patch manually adds the CXL Type-2 additions as a temporary\nmeasure to unblock QEMU development. It should be dropped and\nreplaced with a proper header sync once the kernel series is accepted.\n\nSigned-off-by: Zhi Wang <zhiw@nvidia.com>\nSigned-off-by: Manish Honap <mhonap@nvidia.com>\n---\n linux-headers/linux/vfio.h | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)", "diff": "diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h\nindex 720edfee7a..62cd725a39 100644\n--- a/linux-headers/linux/vfio.h\n+++ b/linux-headers/linux/vfio.h\n@@ -215,6 +215,7 @@ struct vfio_device_info {\n #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6)\t/* vfio-fsl-mc device */\n #define VFIO_DEVICE_FLAGS_CAPS\t(1 << 7)\t/* Info supports caps */\n #define VFIO_DEVICE_FLAGS_CDX\t(1 << 8)\t/* vfio-cdx device */\n+#define VFIO_DEVICE_FLAGS_CXL\t(1 << 9)\t/* vfio-cxl device */\n \t__u32\tnum_regions;\t/* Max region index + 1 */\n \t__u32\tnum_irqs;\t/* Max IRQ index + 1 */\n \t__u32 cap_offset;\t/* Offset within info struct of first cap */\n@@ -257,6 +258,19 @@ struct vfio_device_info_cap_pci_atomic_comp {\n \t__u32 reserved;\n };\n \n+#define VFIO_DEVICE_INFO_CAP_CXL\t\t\t6\n+struct vfio_device_info_cap_cxl {\n+\tstruct vfio_info_cap_header header; /* id=6, version=1 */\n+\t__u8 hdm_regs_bar_index; /* PCI BAR containing CXL component registers */\n+\t__u8 reserved[3];\n+\t__u32 flags; /* VFIO_CXL_CAP_* flags */\n+#define VFIO_CXL_CAP_FIRMWARE_COMMITTED (1 << 0)\n+#define VFIO_CXL_CAP_CACHE_CAPABLE (1 << 1)\n+\t__u64 hdm_regs_offset; /* byte offset within BAR to CXL.mem register area */\n+\t__u32 dpa_region_index; /* VFIO region index for DPA memory */\n+\t__u32 comp_regs_region_index; /* VFIO region index for COMP_REGS */\n+};\n+\n /**\n * VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8,\n *\t\t\t\t struct vfio_region_info)\n@@ -373,6 +387,10 @@ struct vfio_region_info_cap_type {\n /* sub-types for VFIO_REGION_TYPE_GFX */\n #define VFIO_REGION_SUBTYPE_GFX_EDID (1)\n \n+/* sub-types for VFIO CXL regions */\n+#define VFIO_REGION_SUBTYPE_CXL (1) /* DPA memory region */\n+#define VFIO_REGION_SUBTYPE_CXL_COMP_REGS (2) /* HDM register shadow */\n+\n /**\n * struct vfio_region_gfx_edid - EDID region layout.\n *\n", "prefixes": [ "RFC", "3/9" ] }