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GET /api/1.1/patches/2229156/?format=api
{ "id": 2229156, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229156/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-9-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-9-mhonap@nvidia.com>", "date": "2026-04-27T18:12:34", "name": "[RFC,8/9] hw/arm/smmu-common: Allow pxb-cxl as SMMUv3 primary bus", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1e76b1dc1dd5402cdd94f20eee83049b8d966dc9", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-9-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229156/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229156/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Cd/XjHzZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c112::7;\n envelope-from=mhonap@nvidia.com;\n helo=CY3PR05CU001.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 8/9] hw/arm/smmu-common: Allow pxb-cxl as SMMUv3 primary bus", "Date": "Mon, 27 Apr 2026 23:42:34 +0530", "Message-ID": "<20260427181235.3003865-9-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260427181235.3003865-1-mhonap@nvidia.com>", "References": "<20260427181235.3003865-1-mhonap@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FC:EE_|DM6PR12MB4041:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c8aa36e9-57e5-4663-6885-08dea488df16", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|921020|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n A+PgMTlVfr0JqiZxRdAcyq2HQsNV2E+Av7sBmviJamNDoC4vIQhu2Qe2yNnrohAXYrUOokCM5/v24PUHvgsQs/z5NYvQqIKcn+Nswc9yUKmjnvNzgECRCsj+kx2K4vobQZAA/oDWzlEoQ9WYf+mLLfMgpfo/nhzRPw5cs3Q4ZwFJouKYSCd7AkFkZNR3iA7urFl1L2RRYuzQ6f0fj+daObiiQTomdMD685iuHil+HwFKNNu4RQQVBLyPo9fhb9tyBsBVJ+X+G3DkYRKc09CHcB2VzRgGSutLuQeYu1jCQ1yUhwddpa9eVZIU1mdQYzXaeoIWuWrdHFwT0kQzc5HnwcgJf3zOy5rgn8Y5xnqfjVsUai2mKUI92PvwzlRZz/EHisFsI1LduqP/2dnfnBaHL9LUcjrv3ozksalo9N33zFQK+yLB4T6e9F3naUzCKNOdHOLOdBpGcCjAeQHAXPHd7+J13uhpJkAlo7+Hb5O0h/fLMHc3/vXJo89CfW6elqRCUfCM5u+UcLjt2csX/7b090XJQoZTgLnfx42M99btxBl7clxHhBzXwehD7Zb4liOQ2+52CWjPRAgmTIr7mdM3genqKkFP5vNtwJH/6587+WdiFXZ51VeSkCGIR8BbRQdJPe+D7OB8lKLis7KmIUibeDoClyPLxEdl0TSttHdCMGus+LoLWA5+SF/T+mXffdQ90z+YIMqjdwouMaTPNEOB3sKQpKjoUXVIPa+dg9njxrGU/UyR5RmUguIp2DcJZ82/C8O31nicDGEyfquY0mjnZ/ZF7/E8T9CKeJyBETFb5ekKtE1xAeAIbndrT+Cc7VSg", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(921020)(56012099003)(22082099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n /ZjmGiA/lXKWndNkD2yNgYekGH1Yfctloq3Jrm/QyWSWBGe9KjJsbDDULFvAf+9cG0jG9W4qpdhwLL/GG7iw+foQbvLpOHvps4tP0Sfz6Q2vEIyQ86Egr6Pu/SIVeckBfA09iYrtqBLaOLfsqLqJWli/hn8OQE++N6JOK6e378VoHIo/fiCrzNHy8m2PYmZP3LxxH68mxCIIYlhMHev8ksrO6MIL+ccjpYWj853Pl3GjOStCRc/sfFvdR7aHF0/9jrV+iS0dEASxfkCi6a3HrlCcTvuLWF8VW/6+za8/qFqBOu/g9uKy7prNsGfGCtjjUBC15vmSg4kkBDNJE5OrcNApfmt4cvjBMPP7TBsU/epVLXpBss+YKlanYVBBii3S0NE0bf+yx3eSMxml8or7Ur14+2NkVxjlrIzD1BCPkaOzkOLsF3VKSSBXX8bYGKEt", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 18:14:49.6680 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c8aa36e9-57e5-4663-6885-08dea488df16", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4041", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nThe SMMUv3 primary bus check only accepted pxb-pcie as a valid root.\npxb-cxl uses the same PCIe-compatible bus implementation; reject it\nand CXL devices behind it cannot reach the IOMMU.\n\nExtend the check to also accept CXL buses so SMMUv3 translation applies\nto passthrough CXL devices. Update the comment above the check to\nmention pxb-cxl alongside pxb-pcie.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Manish Honap <mhonap@nvidia.com>\n---\n hw/arm/smmu-common.c | 17 ++++++++---------\n 1 file changed, 8 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c\nindex 58c4452b1f..eb52ea1976 100644\n--- a/hw/arm/smmu-common.c\n+++ b/hw/arm/smmu-common.c\n@@ -963,19 +963,18 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)\n s->iommu_ops = &smmu_ops;\n }\n /*\n- * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra\n- * root complexes to be associated with SMMU.\n+ * We only allow the default PCIe root complex (pcie.0) or pxb-pcie /\n+ * pxb-cxl based extra root complexes to be associated with SMMU.\n */\n if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) &&\n object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)) {\n /*\n- * This condition matches either the default pcie.0, pxb-pcie, or\n- * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set.\n- * Currently, we don't allow pxb-cxl as it requires further\n- * verification. Therefore, make sure this is indeed pxb-pcie.\n+ * pcie.0 has no parent_dev; pxb-pcie and pxb-cxl do. Accept both\n+ * bus types explicitly so other root complexes are still rejected.\n */\n if (pci_bus->parent_dev) {\n- if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) {\n+ if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS) &&\n+ !object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_CXL_BUS)) {\n goto out_err;\n }\n }\n@@ -988,8 +987,8 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)\n return;\n }\n out_err:\n- error_setg(errp, \"SMMU should be attached to a default PCIe root complex\"\n- \"(pcie.0) or a pxb-pcie based root complex\");\n+ error_setg(errp, \"SMMU should be attached to a default PCIe root complex \"\n+ \"(pcie.0), a pxb-pcie, or a pxb-cxl based root complex\");\n }\n \n /*\n", "prefixes": [ "RFC", "8/9" ] }