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GET /api/1.1/patches/2229154/?format=api
{ "id": 2229154, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229154/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-8-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-8-mhonap@nvidia.com>", "date": "2026-04-27T18:12:33", "name": "[RFC,7/9] hw/vfio+cxl: Program HDM decoder 0 at machine_done for firmware-committed devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c1afbe08ad4247c16acc0d1fd93cf44f085bb1fc", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-8-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229154/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229154/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=XNQU+xRe;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c001::2;\n envelope-from=mhonap@nvidia.com;\n helo=SJ2PR03CU001.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 7/9] hw/vfio+cxl: Program HDM decoder 0 at machine_done for\n firmware-committed devices", "Date": "Mon, 27 Apr 2026 23:42:33 +0530", "Message-ID": "<20260427181235.3003865-8-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260427181235.3003865-1-mhonap@nvidia.com>", "References": "<20260427181235.3003865-1-mhonap@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD3:EE_|MN0PR12MB5785:EE_", "X-MS-Office365-Filtering-Correlation-Id": "44d258bb-7378-4c58-20d3-08dea488d972", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|82310400026|1800799024|376014|7416014|56012099003|18002099003|22082099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n qtkB/ofjo91XNMEgtFYSmb+IzOWB6cnczaPgpYELVLx+HOcztu3AFyUbA65Z4bU7Ec47SICZ1uVAtpjHuzSgUmyIGuR84tBZzGHmWVezbB5x5IF8gQtWcATtjCpMylyUI5tkF8q4mlZZeXWxg3jk/G/TEizBiUPJ4AwaIENG+aEH7VA7bDc8xvj1ppKwLDAf23L/FNBjicThLfgbwzt9CVwtoPztCKpFCPejCAdTotqxeXMGZlQfrjYgwUT+HT6Q7DES5Eli7qAV7euZ8dZLxOokjQzABA8eSVgDanmFgQaVdP4C5FRkeKgTmUNT0s70OCwDcnA/4AA3+6ZK/nhg5x14T1PCkTXTxX9Mk2/u+YH6kMXfNBC8QPF4z/lOVfCELIdTw6VNx3sU3H0B3dHrWMNB1BmeMJIjZIdDLBwebBGIcB/StagpI6mKAv+4mCRQBCc6iCbtqcbh61Dont32386gLF7XxtPQEmle603gqUkMQXZ7uLQ9t2M3QfSRV9TIdUg5HczW4aaLQzPwWjQdXGYJ7Qc10CK+sVR/vYa2pJW3+Xx2bFk8bkoO0RUxB7Rkh+nVCeDle5dNAL3pyqXhZWlNXSTEbvKR3Ip9PmdMlr/29jHusDMKDW6QBXJuQsEAi37mmJrkxuxMBWyrqfYaO4cBZCzOn/0RZE38ZjX3zgeU+cxYXJCVuIiJgKYnvHyffN8oehTD0I2eOlkyhn9Dq55XISMQNpx2joucwvrY7ASVzvC39QDgJHwdjteIr6/7qzLNbn0wO3qPNz/nwFgefxyBtxnIejF3oyP9whxscrFVjdWThoYweeCbQHGR5sKe", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(7416014)(56012099003)(18002099003)(22082099003)(921020);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n XNB0Pze+VV0f5q1Ysyg02DeTCC/CsyQomWCLlFCDWHNBpm/gpBqjLa2PONhR0LGmcoAB9lGLQnZqHx6z4RLGEGMlGpTtuWg0UIZgPY4RVS1fwIuVmv33M/UCOAEQXUCEoz897ckLvRAPgng3tWuT7fuyP9Ah9B8vHG3dEsuptX7/3ddi8oijSq72aHIiLRC15SjdHVQgA/6vxJ5vIdjT9KVBCcy7XzCutQVIa6iXo9KfftCAUIDO0vNSKsbujUu00SLAQGo+3qmTqS7f7WtCiN/mMHTG8D4fFNViMF/3REw23eKb3w9RUUn6x7zg0P6Un2OwgnsDsrlt7h7z3xbK8euZQSre3qb+YabujnU9D4QzdCCyjyZ8NLA/CLzy6KIRNnk5ePktR7Wcmv9RiCPWgsWgf8lSaYqcT5ZFH1YpZvBRAOxPJVMA0i4ya06b+euj", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 18:14:40.2316 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 44d258bb-7378-4c58-20d3-08dea488d972", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD3.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5785", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nsetup_locked_hdm() runs as a machine_done notifier after all devices\nhave been realized. It programs HDM decoder 0 with the CFMWS base\naddress so the guest can fault into device memory from the first\ninstruction.\n\nThe notifier is only registered when the kernel reports the device as\nfirmware-committed (VFIO_CXL_CAP_FIRMWARE_COMMITTED). The host is\nresponsible for HDM decoder programming; the guest has no mechanism to\nremap host physical address mappings.\n\nThe function uses cxl->fmws_base (set by the optional cxl-fmws-base\ndevice property) if non-zero; otherwise it falls back to the\ncxl_fmws_base global captured by cxl_fmws_set_memmap() during machine\nmemory-map init. If neither is set, it warns and returns without\nprogramming anything.\n\nIf COMMIT_LOCK is set in decoder 0 CTRL at machine_done time (left-over\nfrom a prior FLR?), it is cleared before writing BASE so the subsequent\nwrite is not blocked. COMMIT_LOCK is re-set after programming so the\nhardware enforces the committed base.\n\nread_region() return is checked; failure aborts programming rather than\nleaving ctrl uninitialized. All write_region() failures are propagated.\nThe function exits cleanly rather than leaving the decoder half-programmed.\n\nAdd cxl_fmws_base as a hwaddr global in cxl-host.c (and a stub in\ncxl-host-stubs.c). It is set once by cxl_fmws_set_memmap() and read\nlater at machine_done time.\n\nSigned-off-by: Zhi Wang <zhiw@nvidia.com>\nSigned-off-by: Manish Honap <mhonap@nvidia.com>\n---\n hw/cxl/cxl-host-stubs.c | 2 +\n hw/cxl/cxl-host.c | 8 ++\n hw/vfio/pci.c | 176 +++++++++++++++++++++++++++++++++++++-\n hw/vfio/pci.h | 1 +\n hw/vfio/trace-events | 1 +\n include/hw/cxl/cxl_host.h | 10 +++\n 6 files changed, 196 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c\nindex c015baac81..0294d484c0 100644\n--- a/hw/cxl/cxl-host-stubs.c\n+++ b/hw/cxl/cxl-host-stubs.c\n@@ -17,4 +17,6 @@ hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr)\n };\n void cxl_fmws_update_mmio(void) {};\n \n+hwaddr cxl_fmws_base;\n+\n const MemoryRegionOps cfmws_ops;\ndiff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c\nindex a94b893e99..f7e933f452 100644\n--- a/hw/cxl/cxl-host.c\n+++ b/hw/cxl/cxl-host.c\n@@ -429,11 +429,19 @@ void cxl_fmws_update_mmio(void)\n object_child_foreach_recursive(object_get_root(), cxl_fmws_mmio_map, NULL);\n }\n \n+/*\n+ * GPA base of the first CXL Fixed Memory Window region placed in the memory\n+ * map by cxl_fmws_set_memmap(). Set once at machine memory-map init time.\n+ */\n+hwaddr cxl_fmws_base;\n+\n hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr)\n {\n GSList *cfmws_list, *iter;\n CXLFixedWindow *fw;\n \n+ cxl_fmws_base = base;\n+\n cfmws_list = cxl_fmws_get_all_sorted();\n for (iter = cfmws_list; iter; iter = iter->next) {\n fw = CXL_FMW(iter->data);\ndiff --git a/hw/vfio/pci.c b/hw/vfio/pci.c\nindex 0270de61d2..2595229ea5 100644\n--- a/hw/vfio/pci.c\n+++ b/hw/vfio/pci.c\n@@ -25,6 +25,7 @@\n #include \"hw/core/hw-error.h\"\n #include \"hw/core/iommu.h\"\n #include \"hw/cxl/cxl_component.h\"\n+#include \"hw/cxl/cxl_host.h\"\n #include \"hw/pci/msi.h\"\n #include \"hw/pci/msix.h\"\n #include \"hw/pci/pci_bridge.h\"\n@@ -3016,6 +3017,90 @@ static VFIODeviceOps vfio_pci_ops = {\n /* HDM Decoder BASE_LO: bits [31:28] hold address bits [31:28] */\n #define CXL_HDM_BASE_LO_ADDR_MASK 0xF0000000U\n \n+static bool read_region(VFIORegion *region, uint32_t *val, uint64_t offset)\n+{\n+ VFIODevice *vbasedev = region->vbasedev;\n+ uint32_t le_val;\n+\n+ if (pread(vbasedev->fd, &le_val, sizeof(le_val),\n+ region->fd_offset + offset) != sizeof(le_val)) {\n+ error_report(\"vfio-cxl: pread %s offset 0x%\"PRIx64\" failed: %m\",\n+ vbasedev->name, offset);\n+ return false;\n+ }\n+ /* CXL registers are little-endian; convert to host byte order. */\n+ *val = le32_to_cpu(le_val);\n+ return true;\n+}\n+\n+static bool write_region(VFIORegion *region, uint32_t *val, uint64_t offset)\n+{\n+ VFIODevice *vbasedev = region->vbasedev;\n+ /* CXL registers are little-endian; convert from host byte order. */\n+ uint32_t le_val = cpu_to_le32(*val);\n+\n+ if (pwrite(vbasedev->fd, &le_val, sizeof(le_val),\n+ region->fd_offset + offset) != sizeof(le_val)) {\n+ error_report(\"vfio-cxl: pwrite %s offset 0x%\"PRIx64\" failed: %m\",\n+ vbasedev->name, offset);\n+ return false;\n+ }\n+ return true;\n+}\n+\n+/*\n+ * Direct pread/pwrite MemoryRegionOps for the CXL Component Register shadow.\n+ *\n+ * The generic vfio_region_ops routes guest MMIO through\n+ * vfio_device_io_region_read() which returns EINVAL for vendor region\n+ * index 10 at runtime. The same pread() issued directly via\n+ * region->fd_offset works fine, as vfio_cxl_derive_hdm_info() already does.\n+ *\n+ * The kernel enforces 4-byte aligned, 4-byte accesses on this region;\n+ * valid and impl min/max_access_size are both set to 4 to match.\n+ */\n+static uint64_t vfio_cxl_comp_regs_mr_read(void *opaque, hwaddr addr,\n+ unsigned size)\n+{\n+ VFIORegion *region = opaque;\n+ VFIODevice *vbasedev = region->vbasedev;\n+ uint32_t val = 0xFFFFFFFFU;\n+\n+ if (pread(vbasedev->fd, &val, size,\n+ region->fd_offset + addr) != size) {\n+ error_report(\"vfio-cxl: %s COMP_REGS read at 0x%\"HWADDR_PRIx\n+ \" failed: %m\", vbasedev->name, addr);\n+ }\n+\n+ val = le32_to_cpu(val);\n+ trace_vfio_region_read(vbasedev->name, region->nr, addr, size, val);\n+ return val;\n+}\n+\n+static void vfio_cxl_comp_regs_mr_write(void *opaque, hwaddr addr,\n+ uint64_t data, unsigned size)\n+{\n+ VFIORegion *region = opaque;\n+ VFIODevice *vbasedev = region->vbasedev;\n+ uint32_t val = cpu_to_le32((uint32_t)data);\n+\n+ if (pwrite(vbasedev->fd, &val, size,\n+ region->fd_offset + addr) != size) {\n+ error_report(\"vfio-cxl: %s COMP_REGS write at 0x%\"HWADDR_PRIx\n+ \" failed: %m\", vbasedev->name, addr);\n+ }\n+\n+ trace_vfio_region_write(vbasedev->name, region->nr, addr, data, size);\n+}\n+\n+static const MemoryRegionOps vfio_cxl_comp_regs_mr_ops = {\n+ .read = vfio_cxl_comp_regs_mr_read,\n+ .write = vfio_cxl_comp_regs_mr_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .valid = { .min_access_size = 4, .max_access_size = 4 },\n+ .impl = { .min_access_size = 4, .max_access_size = 4 },\n+};\n+\n bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp)\n {\n VFIODevice *vbasedev = &vdev->vbasedev;\n@@ -3404,6 +3489,78 @@ static bool vfio_cxl_derive_hdm_info(VFIODevice *vbasedev, VFIOCXL *cxl,\n return false;\n }\n \n+/*\n+ * setup_locked_hdm - machine_done notifier that programs HDM decoder 0 with\n+ * the FMWS base address so the guest can access DPA through a stable GPA.\n+ *\n+ * Uses cxl->fmws_base (set by the optional cxl-fmws-base device property) if\n+ * non-zero; otherwise falls back to the cxl_fmws_base global captured by\n+ * cxl_fmws_set_memmap() during machine memory-map init. If neither is set,\n+ * the notifier warns and returns without programming anything.\n+ */\n+static void setup_locked_hdm(Notifier *notifier, void *data)\n+{\n+ VFIOCXL *cxl = container_of(notifier, VFIOCXL, machine_done);\n+ VFIORegion *region = &cxl->comp_regs_region;\n+ MemoryRegion *sys_mem = get_system_memory();\n+ uint64_t hdm_base = cxl->hdm_decoder_offset;\n+ uint32_t base_lo, base_hi, ctrl;\n+\n+ if (!cxl->fmws_base) {\n+ cxl->fmws_base = cxl_fmws_base;\n+ if (!cxl->fmws_base) {\n+ warn_report(\"vfio-cxl %s: CXL FMWS base not available\",\n+ region->vbasedev->name);\n+ return;\n+ }\n+ }\n+\n+ if (!read_region(region, &ctrl,\n+ hdm_base + CXL_HDM_DECODER0_CTRL_OFFSET(0))) {\n+ error_report(\"vfio-cxl: %s failed to read HDM decoder 0 CTRL\",\n+ region->vbasedev->name);\n+ return;\n+ }\n+\n+ /*\n+ * If COMMIT_LOCK (bit 8) is still set in the virtual snapshot the kernel\n+ * should have cleared it during open. Warn and clear it here so the\n+ * subsequent BASE write is not blocked.\n+ */\n+ if (ctrl & CXL_HDM_CTRL_COMMIT_LOCK) {\n+ warn_report(\"vfio-cxl: COMMIT_LOCK set in HDM decoder 0 CTRL at \"\n+ \"machine_done; clearing before programming guest GPA\");\n+ ctrl &= ~CXL_HDM_CTRL_COMMIT_LOCK;\n+ if (!write_region(region, &ctrl,\n+ hdm_base + CXL_HDM_DECODER0_CTRL_OFFSET(0))) {\n+ return;\n+ }\n+ }\n+\n+ base_lo = (uint32_t)(cxl->fmws_base & CXL_HDM_BASE_LO_ADDR_MASK);\n+ base_hi = (uint32_t)(cxl->fmws_base >> 32);\n+ ctrl |= CXL_HDM_CTRL_COMMIT | CXL_HDM_CTRL_COMMIT_LOCK;\n+\n+ if (!write_region(region, &base_lo, hdm_base +\n+ CXL_HDM_DECODER0_BASE_LOW_OFFSET(0)) ||\n+ !write_region(region, &base_hi, hdm_base +\n+ CXL_HDM_DECODER0_BASE_HIGH_OFFSET(0)) ||\n+ !write_region(region, &ctrl, hdm_base +\n+ CXL_HDM_DECODER0_CTRL_OFFSET(0))) {\n+ error_report(\"vfio-cxl: %s failed to program HDM decoder 0\",\n+ region->vbasedev->name);\n+ return;\n+ }\n+\n+ trace_vfio_cxl_locked_hdm(/* name */ region->vbasedev->name,\n+ cxl->fmws_base, base_lo, base_hi, ctrl);\n+\n+ memory_region_transaction_begin();\n+ memory_region_add_subregion(sys_mem, cxl->fmws_base, cxl->region.mem);\n+ memory_region_transaction_commit();\n+ cxl->dpa_in_system_mem = true;\n+}\n+\n static bool vfio_cxl_setup(VFIOPCIDevice *vdev, Error **errp)\n {\n VFIODevice *vbasedev = &vdev->vbasedev;\n@@ -3471,8 +3628,11 @@ static bool vfio_cxl_setup(VFIOPCIDevice *vdev, Error **errp)\n error_setg(errp, \"vfio-cxl: failed to get COMP_REGS region info\");\n return false;\n }\n- ret = vfio_region_setup(OBJECT(vdev), vbasedev, &cxl->comp_regs_region,\n- comp_info->index, \"cxl-comp-regs\", errp);\n+\n+ ret = vfio_region_setup_with_ops(OBJECT(vdev), vbasedev,\n+ &cxl->comp_regs_region,\n+ comp_info->index, \"cxl-comp-regs\",\n+ errp, &vfio_cxl_comp_regs_mr_ops);\n if (ret) {\n error_setg(errp, \"vfio-cxl: failed to set up COMP_REGS region\");\n return false;\n@@ -3486,6 +3646,18 @@ static bool vfio_cxl_setup(VFIOPCIDevice *vdev, Error **errp)\n trace_vfio_cxl_setup_params(vbasedev->name, cxl->hdm_regs_bar_index,\n cxl->hdm_regs_offset, cxl->hdm_regs_size,\n cxl->dpa_size);\n+\n+ /*\n+ * Only pre-program the HDM decoder if the kernel reported the device as\n+ * firmware-committed. Non-committed devices need guest driver involvement\n+ * to commit the decoder; registering the notifier for them would write an\n+ * uncommitted BASE value that the hardware ignores.\n+ */\n+ if (cap->flags & VFIO_CXL_CAP_FIRMWARE_COMMITTED) {\n+ cxl->machine_done.notify = setup_locked_hdm;\n+ qemu_add_machine_init_done_notifier(&cxl->machine_done);\n+ }\n+\n return true;\n }\n \ndiff --git a/hw/vfio/pci.h b/hw/vfio/pci.h\nindex f3906f0c53..5667c6ec17 100644\n--- a/hw/vfio/pci.h\n+++ b/hw/vfio/pci.h\n@@ -133,6 +133,7 @@ typedef struct VFIOCXL {\n bool dpa_in_system_mem;\n VFIORegion region;\n VFIORegion comp_regs_region;\n+ Notifier machine_done;\n } VFIOCXL;\n \n struct VFIOPCIDevice {\ndiff --git a/hw/vfio/trace-events b/hw/vfio/trace-events\nindex 3bced3cebb..174e577837 100644\n--- a/hw/vfio/trace-events\n+++ b/hw/vfio/trace-events\n@@ -202,3 +202,4 @@ vfio_device_detach(const char *name, int group_id) \" (%s) group %d\"\n vfio_cxl_setup_params(const char *name, uint8_t bar, uint64_t hdm_off, uint64_t hdm_sz, uint64_t dpa_sz) \" (%s) hdm_bar=%u hdm_regs_offset=0x%\"PRIx64\" hdm_regs_size=0x%\"PRIx64\" dpa_size=0x%\"PRIx64\n vfio_cxl_put_device(const char *name) \" (%s) removing DPA region from system memory\"\n vfio_cxl_bar_subregion(const char *name, int nr, uint64_t off) \" (%s) BAR%d comp_regs overlay at BAR offset 0x%\"PRIx64\n+vfio_cxl_locked_hdm(const char *name, uint64_t fmws, uint32_t blo, uint32_t bhi, uint32_t ctrl) \" (%s) fmws_base=0x%\"PRIx64\" wrote decoder0 base_lo=0x%08x base_hi=0x%08x ctrl=0x%08x\"\ndiff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h\nindex 21619bb748..f890a5c0b9 100644\n--- a/include/hw/cxl/cxl_host.h\n+++ b/include/hw/cxl/cxl_host.h\n@@ -20,6 +20,16 @@ hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr);\n void cxl_fmws_update_mmio(void);\n GSList *cxl_fmws_get_all_sorted(void);\n \n+/**\n+ * cxl_fmws_base - GPA base of the first CXL Fixed Memory Window region.\n+ *\n+ * Set by cxl_fmws_set_memmap() to the base address it receives (typically\n+ * ROUND_UP(highest_gpa + 1, 256 MiB) on ARM virt). Valid after the\n+ * machine memory-map init callback returns, i.e. at machine_done time.\n+ * Zero when no machine has called cxl_fmws_set_memmap() (stub builds).\n+ */\n+extern hwaddr cxl_fmws_base;\n+\n extern const MemoryRegionOps cfmws_ops;\n \n #endif\n", "prefixes": [ "RFC", "7/9" ] }