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GET /api/1.1/patches/2229151/?format=api
{ "id": 2229151, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229151/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-2-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-2-mhonap@nvidia.com>", "date": "2026-04-27T18:12:27", "name": "[RFC,1/9] hw/arm/virt: Add CXL FMWS PA window for device memory", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4f1beeff4b2121da357e2f5da2e9793cbf22a870", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-2-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229151/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229151/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=hTprHfwT;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::7;\n envelope-from=mhonap@nvidia.com;\n helo=CH4PR04CU002.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 1/9] hw/arm/virt: Add CXL FMWS PA window for device memory", "Date": "Mon, 27 Apr 2026 23:42:27 +0530", "Message-ID": "<20260427181235.3003865-2-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260427181235.3003865-1-mhonap@nvidia.com>", "References": "<20260427181235.3003865-1-mhonap@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FA:EE_|DM4PR12MB6229:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5f1ee2ec-6984-44ca-19ba-08dea488bb7a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|56012099003|22082099003|18002099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n SVknWT/3uAAlsmkynRoGUNwMyxgs55b9FT7lezcfEAQG8cIeUsoSoB8rC1ZlrgXghqUvl8lS3FDxa1ArXx2iS01oaaHJ15v9oNfadqb22D20MeAYbDSZTlwxKGO2/IS+0/hw/mjho/IFI1lQtGlY3q9GuVtikXCxkWqMlgMEYBOjWX2d5Ws/2Eqq7EemR0vA40qQD/3z6zlV1EyK6k+XrHiuYNWyceOx3E2yMY89cBP8Ig3bZ65sYzv9LpolZfPPw9tZQrIrFi5fXqAsU5LbTMP9uThqC5dD1ZNYtUJI4EnTVxM8hBE+yg6ToHfANoYP3sOkR1VERgY2lhe2uws/c5jFCmpKV5zLhkxMQt/Jh2OTdDpzM3vlBO+AOoUoUI1t1mFHW5EAPSl6KNuP+iPGW2V0xI7i0q3cySsRnY8em31IDIE+kX+6rYzzTG3GR8ezQa8g0s9lbNJaZnEcWS9XQKMf+FjNbt7cPaopH6ctiItwmT+Ynz5JJWDua/IATh7Sl1oNNqqNLRk/sy+gAk6NYL9wwyrEOA5HxEXdjJnCzHa5Xoy++Gah861ifFBrsg/yzjIpNjChWZSxLPglkwXl2+fGfmQZOkJXJRuy4a2fBOBNmed3uCNeurOcQXAnXS/e7XXPOY3xVj9J+o0NXbBIaCWlUYrSlhB2hzDvBe/fc2KPUWA8f+s1FPta4ATO8YbF//YuyC4QA2mvCbbtLNAU6qVz5LxI3qqOogVDm0z+HwRPJEtmD9/ChU0X1XyivOsX2NBpnsz7PPLuWhhjy4TpWEAXttM3O0o0qxI+62CUv3zGnJUVG27L8Z/JckfZc7oq", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(82310400026)(36860700016)(376014)(7416014)(1800799024)(56012099003)(22082099003)(18002099003)(921020);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n dGOv429AZwZ4tkxxxKTsZynBZqmVSO5CdSKp4pYEnu9JLm8GwMrLifTbAEXsgRVPWLe2/1jxIGKFQ+banTfa4OhVpeMCOOZ+UvahXa/8hxTmlm/foxK11IZLQ4EjO9OCpDzlySQER4luMYPqzGcMWr3fPbdFNSJ2qwH2kWKYAfyShBu42XepeKKB0bvT1Zosqg+VLLYiWSG1kO0ySCieZt56LFzsvRsui0dub2RXKJl+R9cMj6cTHP9UMVPxBH7qHeNpYqqkZcToimrVdWN1GN7xr37Cs/eDj46lwk3xJu1gE1/1Fv42m3RXcQ+wYcVwi3d2TyORV51ijrfHMsE0e23f/7mm3QPyQCshNIQPD/w4Elcf3EnVH2B0MqdopcIRCwqFtbLi1/rElAojoNGZSl9bdqOo9f9O4GddDZiTja1HP11Y+GNCofW9GuwTG1Hi", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 18:13:49.9247 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5f1ee2ec-6984-44ca-19ba-08dea488bb7a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FA.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6229", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nCXL VFIO passthrough needs a stable guest physical address range for\ndevice memory (DPA) that falls inside a CFMWS entry the guest discovers\nfrom ACPI CEDT. Without a dedicated range in the address map, the HDM\ndecoder has nowhere to point.\n\nAdd VIRT_HIGH_CXL_MMIO immediately after the second PCIe MMIO window.\nIt gets its own highmem_cxl_mmio flag in VirtMachineState rather than\nsharing highmem_cxl, so the two slots are independently controllable\neven though both are currently tied to CXL bridge presence.\n\nThe base and size flow through GPEXConfig.cxl_mmio to\nacpi_dsdt_add_gpex(), which carves out a QWord memory descriptor in the\nfirst CXL root bridge's _CRS. The CFMWS window is system-wide, so only\nthe first CXL bridge gets the descriptor - subsequent ones would\nproduce duplicate resource claims for the same range.\n\nbuild_crs() already emits the bridge's own 64-bit ranges into crs.\nThe CFMWS window is a separate system-wide range, so only that window\nis appended as a new QWord descriptor; the bridge ranges are not\nre-emitted. A warn_report() fires if the CFMWS window overlaps any\nexisting bridge 64-bit range, since that would indicate an address\nlayout conflict.\n\nSigned-off-by: Zhi Wang <zhiw@nvidia.com>\nSigned-off-by: Manish Honap <mhonap@nvidia.com>\n---\n hw/arm/virt-acpi-build.c | 5 +++++\n hw/arm/virt.c | 9 +++++++++\n hw/pci-host/gpex-acpi.c | 40 ++++++++++++++++++++++++++++++++++++++\n include/hw/arm/virt.h | 2 ++\n include/hw/pci-host/gpex.h | 1 +\n 5 files changed, 57 insertions(+)", "diff": "diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 591cfc993c..863e0680fb 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -176,6 +176,11 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,\n cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];\n }\n \n+ if (vms->highmem_cxl) {\n+ cfg.cxl_mmio.base = memmap[VIRT_HIGH_CXL_MMIO].base;\n+ cfg.cxl_mmio.size = memmap[VIRT_HIGH_CXL_MMIO].size;\n+ }\n+\n acpi_dsdt_add_gpex(scope, &cfg);\n QLIST_FOREACH(bus, &vms->bus->child, sibling) {\n if (pci_bus_is_cxl(bus)) {\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ec0d8475ca..fa07819401 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -211,6 +211,8 @@ static const MemMapEntry base_memmap[] = {\n #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512\n #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB)\n \n+#define DEFAULT_HIGH_CXL_MMIO_SIZE DEFAULT_HIGH_PCIE_MMIO_SIZE\n+\n /*\n * Highmem IO Regions: This memory map is floating, located after the RAM.\n * Each MemMapEntry base (GPA) will be dynamically computed, depending on the\n@@ -237,6 +239,11 @@ static MemMapEntry extended_memmap[] = {\n [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },\n /* Second PCIe window */\n [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE },\n+ /*\n+ * CXL FMWS guest PA window - separate from PCIe MMIO so the two are\n+ * independently sizeable. Same default size for now.\n+ */\n+ [VIRT_HIGH_CXL_MMIO] = { 0x0, DEFAULT_HIGH_CXL_MMIO_SIZE },\n /* Any CXL Fixed memory windows come here */\n };\n \n@@ -1724,6 +1731,7 @@ static void create_cxl_host_reg_region(VirtMachineState *vms)\n vms->memmap[VIRT_CXL_HOST].size);\n memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr);\n vms->highmem_cxl = true;\n+ vms->highmem_cxl_mmio = true;\n }\n \n static void create_platform_bus(VirtMachineState *vms)\n@@ -1897,6 +1905,7 @@ static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,\n &vms->highmem_cxl,\n &vms->highmem_ecam,\n &vms->highmem_mmio,\n+ &vms->highmem_cxl_mmio,\n };\n \n assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==\ndiff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c\nindex d9820f9b41..7de57bbc46 100644\n--- a/hw/pci-host/gpex-acpi.c\n+++ b/hw/pci-host/gpex-acpi.c\n@@ -7,6 +7,7 @@\n #include \"hw/pci/pci_bridge.h\"\n #include \"hw/pci/pcie_host.h\"\n #include \"hw/acpi/cxl.h\"\n+#include \"qemu/error-report.h\"\n \n static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,\n Aml *scope, uint8_t bus_num)\n@@ -108,6 +109,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)\n CrsRangeSet crs_range_set;\n CrsRangeEntry *entry;\n int i;\n+ bool first_cxl = true;\n \n /* start to construct the tables for pxb */\n crs_range_set_init(&crs_range_set);\n@@ -161,6 +163,44 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)\n */\n crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,\n cfg->pio.base, 0, 0, 0);\n+ if (is_cxl && first_cxl && cfg->cxl_mmio.size) {\n+ uint64_t cfmws_end = cfg->cxl_mmio.base +\n+ cfg->cxl_mmio.size - 1;\n+\n+ /*\n+ * The CXL Fixed Memory Window (CFMWS) is a system-wide GPA\n+ * range. Only the first CXL root bridge emits the QWord\n+ * descriptor; adding it to every bridge would give the OS\n+ * duplicate resource claims for the same range.\n+ *\n+ * build_crs() has already appended the bridge's own 64-bit\n+ * ranges into crs. Do not copy them again here; only append\n+ * the CFMWS window itself as a new QWord descriptor.\n+ *\n+ * Warn if the CFMWS window overlaps any range already claimed\n+ * by the bridge; in the current address layout they should be\n+ * disjoint, but catch it early if the layout ever changes.\n+ */\n+ for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {\n+ entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges,\n+ i);\n+ if (entry->base <= cfmws_end &&\n+ entry->limit >= cfg->cxl_mmio.base) {\n+ warn_report(\"CXL CFMWS [0x%\"PRIx64\"-0x%\"PRIx64\"] \"\n+ \"overlaps CXL root bridge 64-bit range \"\n+ \"[0x%\"PRIx64\"-0x%\"PRIx64\"]\",\n+ cfg->cxl_mmio.base, cfmws_end,\n+ entry->base, entry->limit);\n+ }\n+ }\n+ aml_append(crs,\n+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,\n+ AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE,\n+ 0x0000, cfg->cxl_mmio.base, cfmws_end, 0x0000,\n+ cfg->cxl_mmio.size));\n+ first_cxl = false;\n+ }\n+\n aml_append(dev, aml_name_decl(\"_CRS\", crs));\n \n if (is_cxl) {\ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 5fcbd1c76f..88bb3c0bdf 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -91,6 +91,7 @@ enum {\n VIRT_CXL_HOST,\n VIRT_HIGH_PCIE_ECAM,\n VIRT_HIGH_PCIE_MMIO,\n+ VIRT_HIGH_CXL_MMIO,\n };\n \n typedef enum VirtIOMMUType {\n@@ -147,6 +148,7 @@ struct VirtMachineState {\n bool highmem;\n bool highmem_compact;\n bool highmem_cxl;\n+ bool highmem_cxl_mmio; /* VIRT_HIGH_CXL_MMIO window; follows highmem_cxl */\n bool highmem_ecam;\n bool highmem_mmio;\n bool highmem_redists;\ndiff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h\nindex 1da9c85bce..a7c2e2edf3 100644\n--- a/include/hw/pci-host/gpex.h\n+++ b/include/hw/pci-host/gpex.h\n@@ -43,6 +43,7 @@ struct GPEXConfig {\n MemMapEntry mmio32;\n MemMapEntry mmio64;\n MemMapEntry pio;\n+ MemMapEntry cxl_mmio;\n int irq;\n PCIBus *bus;\n bool pci_native_hotplug;\n", "prefixes": [ "RFC", "1/9" ] }