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GET /api/1.1/patches/2229150/?format=api
{ "id": 2229150, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229150/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-3-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-3-mhonap@nvidia.com>", "date": "2026-04-27T18:12:28", "name": "[RFC,2/9] cxl: Add preserve_config to pxb-cxl OSC method", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0fdc121b06353fd1ac6fdcf52bf6d1f210dbc2f6", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-3-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229150/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229150/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=rZ3Mkn/e;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c107::1;\n envelope-from=mhonap@nvidia.com;\n helo=PH8PR06CU001.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 2/9] cxl: Add preserve_config to pxb-cxl OSC method", "Date": "Mon, 27 Apr 2026 23:42:28 +0530", "Message-ID": "<20260427181235.3003865-3-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260427181235.3003865-1-mhonap@nvidia.com>", "References": "<20260427181235.3003865-1-mhonap@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FE:EE_|DM6PR12MB4417:EE_", "X-MS-Office365-Filtering-Correlation-Id": "de8bbc39-0d5b-4cbc-a31f-08dea488c1b5", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|921020|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n FM5opkPptdGPgWORofhFDGEpcvwuFFj9/LcSw2nKkuRkRT3+dXzEaE+DFo36iBUOkVWIaGuxVP4aLtsqVe8p8aKsY2aDdTrBQl90d5UvRPHtQXtcVvpdyiC7vQuI47wVDAu3pcVy3bZQAESDWW01WeBnhaVP1Bz9HmqfdNbA0NStUyHB5MNPgX0BUiy3kylZu+R94fdJn4fmWsNYTGketdEKKcSG49GL2NJ3Dl03hAWIN5Anuj2pryqsVwM8Rb8RezPpcU0kqFWtgJH2pGOPN0cmjdCGiC/PmvqsZzEEQj2wMV3a7FWgosD/5StYw9uCIL/kuWw1S67717hrzksSdkI9zfeY2jlm/18lww0e41AQcRpPwNcyILFEb2zIap93DEx1iBYWzU8WCYi54XGJDX43fQB4zIjGSmF9p2Gupv/V5Xchu1g6aTv7hVyKwgD+qQncVwWYv6omjPekh5ggb2sn/3AzPp5E6XLuaJS9B1hwgqsFuolT+cfYSamGbcoDD4iDXwVcotFQyAR2uhq1n/arspgRxjdmdcrRij3guRGA0+px2AtNSZFTi4mfpMpH9DOK1d5pU/hsrcCekj3yis7h6m+hTSNEqr2W0QD6oE4NnQoN/wXw7+bpipCUtJ6tJzMBRIrTFFxC8pWh3TPDUPx5wBEkRUiDhJ1YZGXh1IQeJ7y7Teg8eZeCK5vNOyy78oxH6as8g1PZL2khB7z9a2ZWNmJfqdsG68NQJOT+B5pgZXDVN+yuNP8wjY0E1Rd4d3z1U/bNmEcVzfkdRDiUE8sLhoTqAZf1WkDgGGj1fqMhUzxDk2Ov1bBtULmWY2z3", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(921020)(56012099003)(18002099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n XjWHEylXYABBgHEc9eVsdxRfnutnXmDZhzWqYNrUktW23nZmlGy4T6H7unLmSVcE1lkmn2PBkWubyUcZBhqP78c/uMEfta+7bUjlNyNB9h3Nv6igdexpYiTkZcpmvhPJQ9w4lBA29FwijR10ygYYgg3mi0auqXRYOGEP8woI4QTCzBLIxP9fbUy+iez0kquaUaKcisyZ4/vTOMKiV9TcwtuTZHcrUTA5qrAc3XPyQtT9p2XPRFUCUBNUnvPqb3GI6nT6Bz6dpW9rdUQwzjhNqyMm46YZAiV+seS8XCQlonK3/v3BQKMFApH4FhNmKWCDiKB80jZLlfTVQ12lMsH4tJhrIsJEcpoo5gy3jhoCplc/+u2QasWAKWOUSpDtZ9wQv6pCXpQrfUxgw45/wJmGDFTUkNLPIZ0ll5SxzABP+7VLJNLcqtOrIdN0oLpP00l+", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 18:14:00.3576 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n de8bbc39-0d5b-4cbc-a31f-08dea488c1b5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FE.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4417", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nBefore this patch, pxb-cxl bridges had no _DSM method at all. When the\nOS called _DSM on a CXL host bridge, ACPI returned an error and the OS\ndefaulted to reassigning resources across suspend/resume. On machines\nwhere firmware pre-commits the HDM decoder, that reassignment breaks the\nDPA mapping.\n\nWire preserve_config through GPEXConfig into build_cxl_osc_method() so\npxb-cxl host bridges get a _DSM method that signals the OS to keep\nresource assignments stable when needed. The _DSM function 5 (preserve\nfirmware PCI configuration) is the mechanism used to convey this.\n\nbuild_pci_host_bridge_dsm_method() is promoted from static to exported\nso cxl.c can call it without duplicating the AML.\n\nThe x86 build_cxl_osc_method() call site passes false since x86 does\nnot use firmware-committed HDM decoders.\n\nbuild_cxl_osc_method is renamed to acpi_dsdt_add_cxl_host_bridge_methods\nThe function now appends both the CXL _OSC method and the _DSM method,\nso its old name is misleading. Renamed it to match the pxb-pcie analogue\nacpi_dsdt_add_host_bridge_methods(), making the two root bridge code\npaths symmetric. No AML change.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Manish Honap <mhonap@nvidia.com>\n---\n hw/acpi/cxl-stub.c | 2 +-\n hw/acpi/cxl.c | 4 +++-\n hw/i386/acpi-build.c | 2 +-\n hw/pci-host/gpex-acpi.c | 5 +++--\n include/hw/acpi/cxl.h | 2 +-\n include/hw/pci-host/gpex.h | 1 +\n 6 files changed, 10 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/acpi/cxl-stub.c b/hw/acpi/cxl-stub.c\nindex 15bc21076b..d7c6731975 100644\n--- a/hw/acpi/cxl-stub.c\n+++ b/hw/acpi/cxl-stub.c\n@@ -6,7 +6,7 @@\n #include \"hw/acpi/aml-build.h\"\n #include \"hw/acpi/cxl.h\"\n \n-void build_cxl_osc_method(Aml *dev)\n+void acpi_dsdt_add_cxl_host_bridge_methods(Aml *dev, bool preserve_config)\n {\n g_assert_not_reached();\n }\ndiff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c\nindex f92f7fa3d5..b32740a3e3 100644\n--- a/hw/acpi/cxl.c\n+++ b/hw/acpi/cxl.c\n@@ -23,6 +23,7 @@\n #include \"hw/pci/pci_host.h\"\n #include \"hw/cxl/cxl.h\"\n #include \"hw/cxl/cxl_host.h\"\n+#include \"hw/pci-host/gpex.h\"\n #include \"hw/mem/memory-device.h\"\n #include \"hw/acpi/acpi.h\"\n #include \"hw/acpi/aml-build.h\"\n@@ -320,11 +321,12 @@ static Aml *__build_cxl_osc_method(void)\n return method;\n }\n \n-void build_cxl_osc_method(Aml *dev)\n+void acpi_dsdt_add_cxl_host_bridge_methods(Aml *dev, bool preserve_config)\n {\n aml_append(dev, aml_name_decl(\"SUPP\", aml_int(0)));\n aml_append(dev, aml_name_decl(\"CTRL\", aml_int(0)));\n aml_append(dev, aml_name_decl(\"SUPC\", aml_int(0)));\n aml_append(dev, aml_name_decl(\"CTRC\", aml_int(0)));\n aml_append(dev, __build_cxl_osc_method());\n+ aml_append(dev, build_pci_host_bridge_dsm_method(preserve_config));\n }\ndiff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c\nindex f622b91b76..f66ec8ed24 100644\n--- a/hw/i386/acpi-build.c\n+++ b/hw/i386/acpi-build.c\n@@ -1013,7 +1013,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,\n aml_append(aml_pkg, aml_eisaid(\"PNP0A08\"));\n aml_append(aml_pkg, aml_eisaid(\"PNP0A03\"));\n aml_append(dev, aml_name_decl(\"_CID\", aml_pkg));\n- build_cxl_osc_method(dev);\n+ acpi_dsdt_add_cxl_host_bridge_methods(dev, false);\n } else if (pci_bus_is_express(bus)) {\n aml_append(dev, aml_name_decl(\"_HID\", aml_eisaid(\"PNP0A08\")));\n aml_append(dev, aml_name_decl(\"_CID\", aml_eisaid(\"PNP0A03\")));\ndiff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c\nindex 7de57bbc46..247bd78152 100644\n--- a/hw/pci-host/gpex-acpi.c\n+++ b/hw/pci-host/gpex-acpi.c\n@@ -52,7 +52,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,\n }\n }\n \n-static Aml *build_pci_host_bridge_dsm_method(bool preserve_config)\n+Aml *build_pci_host_bridge_dsm_method(bool preserve_config)\n {\n Aml *method = aml_method(\"_DSM\", 4, AML_NOTSERIALIZED);\n Aml *UUID, *ifctx, *ifctx1, *buf;\n@@ -204,7 +204,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)\n aml_append(dev, aml_name_decl(\"_CRS\", crs));\n \n if (is_cxl) {\n- build_cxl_osc_method(dev);\n+ acpi_dsdt_add_cxl_host_bridge_methods(dev,\n+ cfg->preserve_config);\n } else {\n /* pxb bridges do not have ACPI PCI Hot-plug enabled */\n acpi_dsdt_add_host_bridge_methods(dev, true,\ndiff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h\nindex 8f22c71530..6fe6c9c58d 100644\n--- a/include/hw/acpi/cxl.h\n+++ b/include/hw/acpi/cxl.h\n@@ -24,7 +24,7 @@\n void cxl_build_cedt(GArray *table_offsets, GArray *table_data,\n BIOSLinker *linker, const char *oem_id,\n const char *oem_table_id, CXLState *cxl_state);\n-void build_cxl_osc_method(Aml *dev);\n+void acpi_dsdt_add_cxl_host_bridge_methods(Aml *dev, bool preserve_config);\n void build_cxl_dsm_method(Aml *dev);\n \n #endif\ndiff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h\nindex a7c2e2edf3..e5c2ebef78 100644\n--- a/include/hw/pci-host/gpex.h\n+++ b/include/hw/pci-host/gpex.h\n@@ -73,6 +73,7 @@ struct GPEXHost {\n int gpex_set_irq_num(GPEXHost *s, int index, int gsi);\n \n void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);\n+Aml *build_pci_host_bridge_dsm_method(bool preserve_config);\n void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);\n \n #define PCI_HOST_PIO_BASE \"x-pio-base\"\n", "prefixes": [ "RFC", "2/9" ] }