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GET /api/1.1/patches/2229149/?format=api
{ "id": 2229149, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229149/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-7-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-7-mhonap@nvidia.com>", "date": "2026-04-27T18:12:32", "name": "[RFC,6/9] hw/vfio/pci: Wire CXL component-register BAR with COMP_REGS overlay", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6def33d0688276a42648be4afd411690a0c263e0", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427181235.3003865-7-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229149/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229149/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=MHEPFfhr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c000::1;\n envelope-from=mhonap@nvidia.com;\n helo=BYAPR05CU005.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 6/9] hw/vfio/pci: Wire CXL component-register BAR with COMP_REGS\n overlay", "Date": "Mon, 27 Apr 2026 23:42:32 +0530", "Message-ID": "<20260427181235.3003865-7-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260427181235.3003865-1-mhonap@nvidia.com>", "References": "<20260427181235.3003865-1-mhonap@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD3:EE_|SA1PR12MB6680:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7de79a8d-4308-4b1c-ef7a-08dea488d466", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|1800799024|82310400026|7416014|376014|11006099003|56012099003|22082099003|18002099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n 1di1M7nQ6MNvqMOXuqqBBjoBg/o5lAz3K1kxDGIzBmYA+0ZgcbHLy/PORddAFgdgzDAddaOq12Gp9QCsL4KNeFHc/fxqHc3I21xg27qrmqr11s3hw0jCiMz54zd5Ae6EkdvHYQAwUfzCvQZA+JPkTn4Sr+8VjMM8OvUeW1Wb2y1gFpnHuBAr+OdCSggnyvmUSsRuKe0edx6PFOfegcafzsAEu5YELsX0NwHJyZ99AEjDUpOnucgWjVYDIgizrdygo9S6gviDsHEkigavgM9RlLdb1yKPqyu5Ybr7truOdPV6+h4KxvnGHgtZvsnnnX3JP4G15Hs7OAQTBAoCsHYvR8D6tpmNEDLmTzv0wq4qFOd67emz1HtABnUeCLJWUNly5+hgRt3gYezlQWUZHXmXw6fejAqxfYmx3K6UbY/Zj9gnPQncp5jJ/opjKsrA6TSDvtxW1hfzeglnqC0tjBJT7vlE9r6U0k5Ek/KZ8jcTIkF44jUsSfRp0Xv/1X+qPIKJzoezuQdHxqjtHPR9ObLWEx/cYNvmVy63eZ6LavLW/fjnYpuwYhm2a836A3bOSP4zcVXk4db3CkgimG277iYSow+FPXNfxRUtSftOaLFLSVcCfWZSenNsnElJDbAovguW7RaWui1rHbaN2mrQ2rfCWdAvRGKKcFzWyzTNPrC8yamo5u6ljuWW4an4D9qS9WTscJodPiUpEs3+lN8XORPChcXKbIeDUhz9Mh2esfTESqDffXR2kqM+4tvU1ns6sS2Z7pUQNoDQw1SPY7vdQieJdZQN/KX8d5lcs99bock1TWECCBZIA4Wm4RwA1Ew8A/Nq", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(36860700016)(1800799024)(82310400026)(7416014)(376014)(11006099003)(56012099003)(22082099003)(18002099003)(921020);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n YZmkcU75pTgI/mENTm4hdqpAlX/TalBuX3u9XpWnf3ChY3yfjuML8ZDcTgoEbUZUx1k71arh5cY81zGvmy0vI9QgyK/KR7JRbyw1c7fvVNS7t0eG0htgz/f2K24MGQ0CZ0P4o5E3/2LMk4P1GGBuDwrCVlnzrNSXV6nQurESdTNcEppZ0hzynvonV1Px/ZFsvurp6Wiq+81E01zBdvEMZ5ngak28w6xHO7XtMRe3ynMygfspKwgZWN+TiAHoZRPWFFRr27IZ59oAu8fR/oH13+NQz8JpbeuB4pqG92WLIFBKKnEt5kp92BT5Smzg3yr8Peyr06Oi3VK5np1VDw7eXecLYpfrcC//Q0PaRy2dc7Txz8F9XvFJ5hrPoVS1umgDdL9s2lNOv8pYKTUEOV49P01/ktp9ovfLhKDgzMrAkC7k2jTSJ7jfEKsiEME+yyjG", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 18:14:31.8418 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7de79a8d-4308-4b1c-ef7a-08dea488d466", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD3.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB6680", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nThe CXL Component Register BAR contains two types of ranges that need\ndifferent handling:\n\n - Accelerator register windows: passed through as direct hardware\n mmaps for performance. The kernel reports the real BAR size and\n lists mmappable windows via VFIO_REGION_INFO_CAP_SPARSE_MMAP,\n excluding the HDM Decoder Capability block. vfio_region_mmap()\n creates hardware-backed sub-regions for each sparse area.\n\n - HDM Decoder Capability block: guest accesses must go through\n emulated ops so QEMU can observe and program decoder state. The\n kernel blocks direct mmap of this range.\n\nvfio_bar_register(): after the normal mmap path, overlay the COMP_REGS\nemulation region at hdm_regs_offset with priority 1. In QEMU's\nMemoryRegion model, overlapping subregions are resolved by priority;\nthe default is 0. Priority 1 ensures guest accesses to the HDM range\nalways dispatch through the emulated COMP_REGS ops regardless of any\nhardware-backed sub-region at a neighbouring offset.\n\nvfio_pci_bars_exit(): remove the COMP_REGS overlay before the normal\nBAR teardown path.\n\nSigned-off-by: Zhi Wang <zhiw@nvidia.com>\nSigned-off-by: Manish Honap <mhonap@nvidia.com>\n---\n hw/vfio/pci.c | 26 ++++++++++++++++++++++++++\n hw/vfio/trace-events | 1 +\n 2 files changed, 27 insertions(+)", "diff": "diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c\nindex 49ac661eb3..0270de61d2 100644\n--- a/hw/vfio/pci.c\n+++ b/hw/vfio/pci.c\n@@ -1960,6 +1960,10 @@ static void vfio_bar_register(VFIOPCIDevice *vdev, int nr)\n return;\n }\n \n+ bool cxl_comp_regs_bar = (vdev->vbasedev.flags & VFIO_DEVICE_FLAGS_CXL) &&\n+ nr == vdev->cxl.hdm_regs_bar_index &&\n+ vdev->cxl.comp_regs_region.mem;\n+\n bar->mr = g_new0(MemoryRegion, 1);\n name = g_strdup_printf(\"%s base BAR %d\", vdev->vbasedev.name, nr);\n memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size);\n@@ -1974,6 +1978,21 @@ static void vfio_bar_register(VFIOPCIDevice *vdev, int nr)\n }\n }\n \n+ if (cxl_comp_regs_bar) {\n+ /*\n+ * Overlay the COMP_REGS emulation at hdm_regs_offset with priority 1.\n+ * The kernel excludes the HDM Decoder Capability block from the\n+ * sparse-mmap list, so vfio_region_mmap() creates hardware-backed\n+ * sub-regions only for accelerator register windows. The emulated\n+ * COMP_REGS region sits above those at priority 1, ensuring guest\n+ * accesses to the HDM range always dispatch through the emulated ops.\n+ */\n+ memory_region_add_subregion_overlap(bar->mr, vdev->cxl.hdm_regs_offset,\n+ vdev->cxl.comp_regs_region.mem, 1);\n+ trace_vfio_cxl_bar_subregion(vdev->vbasedev.name, nr,\n+ vdev->cxl.hdm_regs_offset);\n+ }\n+\n pci_register_bar(pdev, nr, bar->type, bar->mr);\n }\n \n@@ -1993,9 +2012,16 @@ void vfio_pci_bars_exit(VFIOPCIDevice *vdev)\n \n for (i = 0; i < PCI_ROM_SLOT; i++) {\n VFIOBAR *bar = &vdev->bars[i];\n+ bool use_comp_regs = (vdev->vbasedev.flags & VFIO_DEVICE_FLAGS_CXL) &&\n+ i == vdev->cxl.hdm_regs_bar_index &&\n+ vdev->cxl.comp_regs_region.mem;\n \n vfio_bar_quirk_exit(vdev, i);\n vfio_region_exit(&bar->region);\n+ if (use_comp_regs && bar->mr) {\n+ memory_region_del_subregion(bar->mr,\n+ vdev->cxl.comp_regs_region.mem);\n+ }\n if (bar->region.size) {\n memory_region_del_subregion(bar->mr, bar->region.mem);\n }\ndiff --git a/hw/vfio/trace-events b/hw/vfio/trace-events\nindex 3678481a8e..3bced3cebb 100644\n--- a/hw/vfio/trace-events\n+++ b/hw/vfio/trace-events\n@@ -201,3 +201,4 @@ vfio_device_detach(const char *name, int group_id) \" (%s) group %d\"\n # pci.c CXL Type-2 passthrough\n vfio_cxl_setup_params(const char *name, uint8_t bar, uint64_t hdm_off, uint64_t hdm_sz, uint64_t dpa_sz) \" (%s) hdm_bar=%u hdm_regs_offset=0x%\"PRIx64\" hdm_regs_size=0x%\"PRIx64\" dpa_size=0x%\"PRIx64\n vfio_cxl_put_device(const char *name) \" (%s) removing DPA region from system memory\"\n+vfio_cxl_bar_subregion(const char *name, int nr, uint64_t off) \" (%s) BAR%d comp_regs overlay at BAR offset 0x%\"PRIx64\n", "prefixes": [ "RFC", "6/9" ] }