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GET /api/1.1/patches/2229144/?format=api
HTTP 200 OK
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{
    "id": 2229144,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229144/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427-qom-tests-v1-38-c413f3605311@redhat.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260427-qom-tests-v1-38-c413f3605311@redhat.com>",
    "date": "2026-04-27T19:42:37",
    "name": "[38/41] target/riscv: fix general_user_opts hash table leak",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "72fb9fc47cafc66a4b669eb885be59c130bb5dd1",
    "submitter": {
        "id": 66774,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/66774/?format=api",
        "name": "Marc-André Lureau",
        "email": "marcandre.lureau@redhat.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427-qom-tests-v1-38-c413f3605311@redhat.com/mbox/",
    "series": [
        {
            "id": 501716,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501716/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501716",
            "date": "2026-04-27T19:42:03",
            "name": "Fix various QOM object life-cycle issues",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501716/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2229144/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2229144/checks/",
    "tags": {},
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        ],
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        "From": "=?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>",
        "Date": "Mon, 27 Apr 2026 23:42:37 +0400",
        "Subject": "[PATCH 38/41] target/riscv: fix general_user_opts hash table leak",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "8bit",
        "Message-Id": "<20260427-qom-tests-v1-38-c413f3605311@redhat.com>",
        "References": "<20260427-qom-tests-v1-0-c413f3605311@redhat.com>",
        "In-Reply-To": "<20260427-qom-tests-v1-0-c413f3605311@redhat.com>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "armbru@redhat.com,\n =?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>,\n  Palmer Dabbelt <palmer@dabbelt.com>,\n  Alistair Francis <alistair.francis@wdc.com>,\n  Weiwei Li <liwei1518@gmail.com>,\n  Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n  Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n  Chao Liu <chao.liu.zevorn@gmail.com>, qemu-riscv@nongnu.org",
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    },
    "content": "The global general_user_opts hash table is recreated on every\nriscv_cpu_init() call, leaking the previous one. Clear any existing\ntable before creating a new one, and destroy it on CPU finalization.\n\nFixes: d167a2247ede (\"target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]\")\nSigned-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>\n---\n target/riscv/cpu.c | 7 +++++++\n 1 file changed, 7 insertions(+)",
    "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 8ac935ac06e..15fa03e22a4 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -1101,6 +1101,7 @@ static void riscv_cpu_init(Object *obj)\n                             \"riscv.cpu.rnmi\", RNMI_MAX);\n #endif /* CONFIG_USER_ONLY */\n \n+    g_clear_pointer(&general_user_opts, g_hash_table_destroy);\n     general_user_opts = g_hash_table_new(g_str_hash, g_str_equal);\n \n     /*\n@@ -2961,6 +2962,11 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)\n     DEFINE_RISCV_CPU(type_name, parent_type_name,             \\\n         .profile = &(profile_))\n \n+static void riscv_cpu_instance_finalize(Object *obj)\n+{\n+    g_clear_pointer(&general_user_opts, g_hash_table_destroy);\n+}\n+\n static const TypeInfo riscv_cpu_type_infos[] = {\n     {\n         .name = TYPE_RISCV_CPU,\n@@ -2968,6 +2974,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n         .instance_size = sizeof(RISCVCPU),\n         .instance_align = __alignof(RISCVCPU),\n         .instance_init = riscv_cpu_init,\n+        .instance_finalize = riscv_cpu_instance_finalize,\n         .abstract = true,\n         .class_size = sizeof(RISCVCPUClass),\n         .class_init = riscv_cpu_common_class_init,\n",
    "prefixes": [
        "38/41"
    ]
}