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GET /api/1.1/patches/2228944/?format=api
{ "id": 2228944, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228944/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260427-nord-tlmm-v2-1-ade8e0f3d803@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427-nord-tlmm-v2-1-ade8e0f3d803@oss.qualcomm.com>", "date": "2026-04-27T14:00:29", "name": "[v2,1/2] dt-bindings: pinctrl: describe the Qualcomm nord-tlmm", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4b1c12b289bbd440c86e8496c489d42fa37e1ecc", "submitter": { "id": 92196, "url": "http://patchwork.ozlabs.org/api/1.1/people/92196/?format=api", "name": "Bartosz Golaszewski", "email": "bartosz.golaszewski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260427-nord-tlmm-v2-1-ade8e0f3d803@oss.qualcomm.com/mbox/", "series": [ { "id": 501657, "url": "http://patchwork.ozlabs.org/api/1.1/series/501657/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501657", "date": "2026-04-27T14:00:28", "name": "pinctrl: qcom: add support for the TLMM controller on Nord platforms", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501657/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228944/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228944/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35584-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=dyU6p2XW;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=AXBXKoT2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260427-nord-tlmm-v2-1-ade8e0f3d803@oss.qualcomm.com>", "References": "<20260427-nord-tlmm-v2-0-ade8e0f3d803@oss.qualcomm.com>", "In-Reply-To": "<20260427-nord-tlmm-v2-0-ade8e0f3d803@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Richard Cochran <richardcochran@gmail.com>,\n Bartosz Golaszewski <brgl@kernel.org>,\n Shawn Guo <shengchao.guo@oss.qualcomm.com>,\n Arnd Bergmann <arnd@arndb.de>,\n Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n netdev@vger.kernel.org,\n Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=9299;\n i=bartosz.golaszewski@oss.qualcomm.com; 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a=openpgp;\n fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI3MDE0OSBTYWx0ZWRfX072N2L5YicPo\n tVRm4Ks5IYbezFXDlRtk2NCQRkQ6j/YCoRGV4O6NhizDe2H4C1YIY18DrCvIx3m5KPTec3hqeHk\n g4cSYboyxVSUfBoVJoeXgv7XTXdh5GZG112/vTGlZ6xZT32MAVIgcA4mnNjV1Hv3cjj1vFYZtXR\n 6dBG3oZ5saMW6GQhxYKxADxQDVdqqPxM5ZP76vX6u04dl8hD8IAS1ccsE7ki7SHmrf9fjwtt2cI\n 3HV6/TLOH4986vw0rFNnB9kGS6QbdP5FkAa6qmE/npUpZN2B8EhghFzBgca1of7xfgYJ4s/VX13\n wgyDgm9VM55V4frDs/Z4O0i+LEFidqyHwp0jj1D+BQrWlgAh4jSqIzed0acrFLTRTuNsq+/+94l\n RqqblWcjCBw0cjoeEodS3SFMROwJbyISnvzDar5DJVn4FrFuWpcknbeQ0ferVuqzSc0crqph4yc\n HstxRIeCq+ghMAPiSpA==", "X-Proofpoint-ORIG-GUID": "4p8J9epzmOdxpMAwZnlSG-ablZZPsEUw", "X-Authority-Analysis": "v=2.4 cv=AJEsYPsu c=1 sm=1 tr=0 ts=69ef6c0e cx=c_pps\n a=4ztaESFFfuz8Af0l9swBwA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=gEfo2CItAAAA:8\n a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=NwY9oKpC6fpBCectsZUA:9 a=QEXdDO2ut3YA:10\n a=TPnrazJqx2CeVZ-ItzZ-:22 a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-GUID": "4p8J9epzmOdxpMAwZnlSG-ablZZPsEUw", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-27_04,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n phishscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0\n malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270149" }, "content": "Add a DT binding document describing the TLMM pin controller available\non the Nord platforms from Qualcomm.\n\nCo-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\nSigned-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\nSigned-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>\n---\n .../bindings/pinctrl/qcom,nord-tlmm.yaml | 184 +++++++++++++++++++++\n 1 file changed, 184 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b776dd20e15b6cfd3d99c7b96cf23733ada817bc\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml\n@@ -0,0 +1,184 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Technologies, Inc. SA8797P TLMM block\n+\n+maintainers:\n+ - Bartosz Golaszewski <brgl@kernel.org>\n+\n+description:\n+ Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,nord-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 90\n+\n+ gpio-line-names:\n+ maxItems: 181\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-nord-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-nord-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-nord-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$\"\n+ - enum: [ ufs_reset ]\n+ minItems: 1\n+ maxItems: 16\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,\n+ atest_char_start, atest_usb20, atest_usb21, aud_intfc0_clk,\n+ aud_intfc0_data0, aud_intfc0_data1, aud_intfc0_data2,\n+ aud_intfc0_data3, aud_intfc0_data4, aud_intfc0_data5,\n+ aud_intfc0_data6, aud_intfc0_data7, aud_intfc0_ws,\n+ aud_intfc10_clk, aud_intfc10_data0, aud_intfc10_data1,\n+ aud_intfc10_ws, aud_intfc1_clk, aud_intfc1_data0,\n+ aud_intfc1_data1, aud_intfc1_data2, aud_intfc1_data3,\n+ aud_intfc1_data4, aud_intfc1_data5, aud_intfc1_data6,\n+ aud_intfc1_data7, aud_intfc1_ws, aud_intfc2_clk,\n+ aud_intfc2_data0, aud_intfc2_data1, aud_intfc2_data2,\n+ aud_intfc2_data3, aud_intfc2_ws, aud_intfc3_clk,\n+ aud_intfc3_data0, aud_intfc3_data1, aud_intfc3_ws,\n+ aud_intfc4_clk, aud_intfc4_data0, aud_intfc4_data1,\n+ aud_intfc4_ws, aud_intfc5_clk, aud_intfc5_data0,\n+ aud_intfc5_data1, aud_intfc5_ws, aud_intfc6_clk,\n+ aud_intfc6_data0, aud_intfc6_data1, aud_intfc6_ws,\n+ aud_intfc7_clk, aud_intfc7_data0, aud_intfc7_data1,\n+ aud_intfc7_ws, aud_intfc8_clk, aud_intfc8_data0,\n+ aud_intfc8_data1, aud_intfc8_ws, aud_intfc9_clk,\n+ aud_intfc9_data0, aud_intfc9_ws, aud_mclk0_mira,\n+ aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,\n+ aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,\n+ bist_done, ccu_async_in0, ccu_async_in1, ccu_async_in2,\n+ ccu_async_in3, ccu_async_in4, ccu_async_in5, ccu_i2c_scl0,\n+ ccu_i2c_scl1, ccu_i2c_scl2, ccu_i2c_scl3, ccu_i2c_scl4,\n+ ccu_i2c_scl5, ccu_i2c_scl6, ccu_i2c_scl7, ccu_i2c_scl8,\n+ ccu_i2c_scl9, ccu_i2c_sda0, ccu_i2c_sda1, ccu_i2c_sda2,\n+ ccu_i2c_sda3, ccu_i2c_sda4, ccu_i2c_sda5, ccu_i2c_sda6,\n+ ccu_i2c_sda7, ccu_i2c_sda8, ccu_i2c_sda9, ccu_timer0,\n+ ccu_timer1, ccu_timer10, ccu_timer11, ccu_timer12, ccu_timer13,\n+ ccu_timer14, ccu_timer15, ccu_timer2, ccu_timer3, ccu_timer4,\n+ ccu_timer5, ccu_timer6, ccu_timer7, ccu_timer8, ccu_timer9,\n+ clink_debug, dbg_out, dbg_out_clk, ddr_bist_complete,\n+ ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,\n+ ddr_pxi1, ddr_pxi10, ddr_pxi11, ddr_pxi12, ddr_pxi13, ddr_pxi14,\n+ ddr_pxi15, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6,\n+ ddr_pxi7, ddr_pxi8, ddr_pxi9, dp_rx0, dp_rx00, dp_rx01,\n+ dp_rx0_mute, dp_rx1, dp_rx10, dp_rx11, dp_rx1_mute, edp0_hot,\n+ edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot,\n+ edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,\n+ emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg0, emac1_mcg1,\n+ emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_ptp,\n+ gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,\n+ gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,\n+ mbist_pass, mdp0_vsync0_out, mdp0_vsync10_out, mdp0_vsync1_out,\n+ mdp0_vsync2_out, mdp0_vsync3_out, mdp0_vsync4_out,\n+ mdp0_vsync5_out, mdp0_vsync6_out, mdp0_vsync7_out,\n+ mdp0_vsync8_out, mdp0_vsync9_out, mdp1_vsync0_out,\n+ mdp1_vsync10_out, mdp1_vsync1_out, mdp1_vsync2_out,\n+ mdp1_vsync3_out, mdp1_vsync4_out, mdp1_vsync5_out,\n+ mdp1_vsync6_out, mdp1_vsync7_out, mdp1_vsync8_out,\n+ mdp1_vsync9_out, mdp_vsync_e, mdp_vsync_p, mdp_vsync_s,\n+ pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,\n+ pcie3_clk_req_n, phase_flag0, phase_flag1, phase_flag10,\n+ phase_flag11, phase_flag12, phase_flag13, phase_flag14,\n+ phase_flag15, phase_flag16, phase_flag17, phase_flag18,\n+ phase_flag19, phase_flag2, phase_flag20, phase_flag21,\n+ phase_flag22, phase_flag23, phase_flag24, phase_flag25,\n+ phase_flag26, phase_flag27, phase_flag28, phase_flag29,\n+ phase_flag3, phase_flag30, phase_flag31, phase_flag4,\n+ phase_flag5, phase_flag6, phase_flag7, phase_flag8,\n+ phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,\n+ pwrbrk_i_n, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,\n+ qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,\n+ qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,\n+ qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qspi0, qspi1,\n+ qspi2, qspi3, qspi_clk, qspi_cs0_n, qspi_cs1_n,\n+ qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,\n+ qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,\n+ qup1_se6,\n+ qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, qup2_se5,\n+ qup2_se6,\n+ qup3_se0_mira, qup3_se0_mirb,\n+ sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,\n+ smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,\n+ tmess_prng1, tsc_timer0, tsc_timer1, tsc_timer2, tsc_timer3,\n+ tsc_timer4, tsc_timer5, tsc_timer6, tsc_timer7, tsc_timer8,\n+ tsc_timer9, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,\n+ tsense_pwm5, tsense_pwm6, tsense_pwm7, tsense_pwm8, usb0_hs,\n+ usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,\n+ usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@f100000 {\n+ compatible = \"qcom,nord-tlmm\";\n+ reg = <0x0f100000 0xc0000>;\n+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-ranges = <&tlmm 0 0 181>;\n+ wakeup-parent = <&pdc>;\n+\n+ qup_uart15_default: qup-uart15-default-state {\n+ pins = \"gpio147\", \"gpio148\";\n+ function = \"qup2_se2\";\n+ drive-strength = <2>;\n+ bias-disable;\n+ };\n+ };\n+...\n", "prefixes": [ "v2", "1/2" ] }