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GET /api/1.1/patches/2228921/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
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{
    "id": 2228921,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228921/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260427135819.2577234-2-andre.przywara@arm.com/",
    "project": {
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        "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
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    },
    "msgid": "<20260427135819.2577234-2-andre.przywara@arm.com>",
    "date": "2026-04-27T13:58:18",
    "name": "[v3,1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "46617f72fedffa2c2f6255e1c4b66147b41c65bb",
    "submitter": {
        "id": 61837,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/61837/?format=api",
        "name": "Andre Przywara",
        "email": "andre.przywara@arm.com"
    },
    "delegate": {
        "id": 114289,
        "url": "http://patchwork.ozlabs.org/api/1.1/users/114289/?format=api",
        "username": "apritzel",
        "first_name": "Andre",
        "last_name": "Przywara",
        "email": "andre.przywara@arm.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260427135819.2577234-2-andre.przywara@arm.com/mbox/",
    "series": [
        {
            "id": 501653,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501653/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501653",
            "date": "2026-04-27T13:58:17",
            "name": "sunxi: H616: DRAM: Fix TPR6 parameter parsing",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/501653/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2228921/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2228921/checks/",
    "tags": {},
    "headers": {
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        "From": "Andre Przywara <andre.przywara@arm.com>",
        "To": "u-boot@lists.denx.de",
        "Cc": "Jernej Skrabec <jernej.skrabec@gmail.com>,\n Philippe Simons <simons.philippe@gmail.com>,\n Paul Kocialkowski <paulk@sys-base.io>, linux-sunxi@lists.linux.dev,\n Mikhail Kalashnikov <iuncuim@gmail.com>,\n Cody Eksal <masterr3c0rd@epochal.quest>",
        "Subject": "[PATCH v3 1/2] sunxi: H616: dram: fix LPDDR3 TPR6 parsing",
        "Date": "Mon, 27 Apr 2026 15:58:18 +0200",
        "Message-ID": "<20260427135819.2577234-2-andre.przywara@arm.com>",
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        "In-Reply-To": "<20260427135819.2577234-1-andre.przywara@arm.com>",
        "References": "<20260427135819.2577234-1-andre.przywara@arm.com>",
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    "content": "From: Jernej Skrabec <jernej.skrabec@gmail.com>\n\nAllwinner's DRAM initialisation code defines a parameter named TPR6,\npresumably containing some \"Vref\" parameter, but containing values for\n*all* DRAM types. The runtime code selects one byte based on the DRAM\ntype used.\nThis selection code was wrong for LPDDR3, the value is encoded in\nbits [23:16], not [15:8]. Fix that in the code, which also aligns it\nwith the very similar code for the A133 and A523.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>\nReported-by: Philippe Simons <simons.philippe@gmail.com>\nReviewed-by: Andre Przywara <andre.przywara@arm.com>\n---\n arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)",
    "diff": "diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c\nindex 3345c9b8e82..42a0550e015 100644\n--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c\n+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c\n@@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para,\n \t\tval = para->tpr6 & 0xff;\n \t\tbreak;\n \tcase SUNXI_DRAM_TYPE_LPDDR3:\n-\t\tval = para->tpr6 >> 8 & 0xff;\n+\t\tval = para->tpr6 >> 16 & 0xff;\n \t\tbreak;\n \tcase SUNXI_DRAM_TYPE_LPDDR4:\n \t\tval = para->tpr6 >> 24 & 0xff;\n",
    "prefixes": [
        "v3",
        "1/2"
    ]
}