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GET /api/1.1/patches/2228913/?format=api
{ "id": 2228913, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228913/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260427134231.531222-7-pshete@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427134231.531222-7-pshete@nvidia.com>", "date": "2026-04-27T13:42:31", "name": "[v3,6/6] arm64: tegra: Add pinctrl nodes for Tegra264", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1ba01c6e3b6e1eaaff18af129c74c7e7894f59e1", "submitter": { "id": 82424, "url": "http://patchwork.ozlabs.org/api/1.1/people/82424/?format=api", "name": "Prathamesh Shete", "email": "pshete@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260427134231.531222-7-pshete@nvidia.com/mbox/", "series": [ { "id": 501651, "url": "http://patchwork.ozlabs.org/api/1.1/series/501651/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501651", "date": "2026-04-27T13:42:25", "name": "Add Tegra238 and Tegra264 pinctrl support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501651/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228913/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228913/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35571-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "<pshete@nvidia.com>", "To": "<linusw@kernel.org>, <thierry.reding@kernel.org>, <pshete@nvidia.com>,\n\t<jonathanh@nvidia.com>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>", "CC": "<webgeek1234@gmail.com>, <rosenp@gmail.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-gpio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>", "Subject": "[PATCH v3 6/6] arm64: tegra: Add pinctrl nodes for Tegra264", "Date": "Mon, 27 Apr 2026 13:42:31 +0000", "Message-ID": "<20260427134231.531222-7-pshete@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427134231.531222-1-pshete@nvidia.com>", "References": "<20260427134231.531222-1-pshete@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": 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"\n\tjMDaluLuN8dMANj902N7LnRh1Wrqt31C9Q6zDKdfRuwKZSyHPEwrla9gLGCqymRF0g5m8Mz29I8KmewggUtI2QTDfF018UE6Eyq0ZmwBbtomJGAi2NPl0axYOK4xe4wEtHkv7xAoGZVUnlh9K8sDEUYP12IVnkJvu3lOvnMn76hSUumU/KD3x7pSLFSzmIwMtYYxCbOHiSaaPyAD8ukythT/aqEYrOlDv01j9Ioq+fzRhxD5zmHSdyh2OWEg9LpIKcHJRhTSqKHYeOgkefJZ7gpRwSAJebXB+UQnZ/lgLK3MIYjlvfTArF0bANdRZNssd1tMD7+m/ye3PEcisnYD+CYD6AhelwU6x1AGMHZBaf3NTs5KT3q+MbOwGHzvfWx+fmAnzyOt8RAro6oEmcfUqLhNqewOxFPuiTS96DCfOyq5uZ0ShfKqRozNXAAUPL2fomacejvpmoa7Lr76DU37cQseJFZ2TDM4w6uoYjpt0fRMMg2yRvBH48+F71Tu1aDVRkyepDvpcqYMcgfKGlXq9Cf/Lb1OtvVZ96RQZgjl5qDqukzQtcatsfreoBkYSNvv5Oz24EttpuTiejivpB0F1mX3YtnpA2MF/MDuCCDqfo2h7UOhbc+m7CVrFyE5OKYSW82YY/37COUqOC7EJLzcGwqNwsKhQBuYB4JoMXnyzt0MvaYMmpddTxZ9gHPgeFcDh7i3FdO1LLTwFa5ERVdmbwBC1PvMU8MHsA+rFAx3qADZOxArIBjkb0RW1Wot5k2B+fsoTyY0HiG6Zw2/EH+o9g==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tdWZTOsSLBKyQYCWXVVv062K0KexEqMVeMqpcJQSIYXfuPaHOeJhifpgKxJpt5OwCS2j1R09Qqpz1pnTvBZwwRof0fjrY4nyHeJ/Vx97WisTKb7fVPPxe1QuhyjiMoCwBQuIboFcGU7YWZeC6CGAtgq3Bq4l7PN0XsKnt6opTDft3osLmqZeackT9hDoHPiNvdYtB8mrTOHfsEbyQCsBTVTrcDB6xR2bfofpuIi9jN83IUDvZ+UiJXOeE3KKpGTKZwi5Q4jTruvc4iPzdUbYwx4/f9SkL7kugK6wZZG/Kx0rl5dzbL86o7nKFN1mbrNkfEYLx2dEhhtJMcBTqQNYulvbxPqbU115uk7toFgcE8PrjPtuQygzM4McNrazu7Qp54J7AdSZH6vbUqxM9+yTsCstCwYrtpy3saFZgSTHeESoV+xL8jOP/ibIrjNUK3d1l", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 13:43:53.0886\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2441411b-db9f-492f-4798-08dea4630562", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023CB.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB6442" }, "content": "From: Prathamesh Shete <pshete@nvidia.com>\n\nAdd the three pin controller (MAIN, UPHY, AON) device-tree nodes found on\nTegra264.\n\nSigned-off-by: Prathamesh Shete <pshete@nvidia.com>\n---\nChanges in v3:\n - Wrap commit message to 75 chars per line (v2 was too short).\nChanges in v2:\n - This patch is added as part of v2.\n---\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\nindex 06d8357bdf52..dc7793088d2e 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n@@ -3380,6 +3380,11 @@ i2c3: i2c@c610000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpinmux_aon: pinmux@c7a2000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pinmux-aon\";\n+\t\t\treg = <0x0 0x0c7a2000 0x0 0x2000>;\n+\t\t};\n+\n \t\tpmc: pmc@c800000 {\n \t\t\tcompatible = \"nvidia,tegra264-pmc\";\n \t\t\treg = <0x0 0x0c800000 0x0 0x100000>,\n@@ -3586,6 +3591,11 @@ pci@c000000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpinmux_main: pinmux@c281000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pinmux-main\";\n+\t\t\treg = <0x00 0x0c281000 0x0 0xc000>;\n+\t\t};\n+\n \t\ti2c14: i2c@c410000 {\n \t\t\tcompatible = \"nvidia,tegra264-i2c\";\n \t\t\treg = <0x00 0x0c410000 0x0 0x10000>;\n@@ -3862,6 +3872,11 @@ bus@a800000000 {\n \t\t\t <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */\n \t\t\t <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */\n \n+\t\tpinmux_uphy: pinmux@82e0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pinmux-uphy\";\n+\t\t\treg = <0x00 0x082e0000 0x0 0x4000>;\n+\t\t};\n+\n \t\tgpio_uphy: gpio@8300000 {\n \t\t\tcompatible = \"nvidia,tegra264-gpio-uphy\";\n \t\t\treg = <0x00 0x08300000 0x0 0x2000>,\n", "prefixes": [ "v3", "6/6" ] }