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GET /api/1.1/patches/2228881/?format=api
{ "id": 2228881, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228881/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-15-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-15-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:48", "name": "[PULL,14/63] hw/arm/fsl-imx8mm: Adding support for ENET ethernet controller", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "76315e00e90842d705aa8ea98c25e73328917049", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-15-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228881/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228881/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=jpfGwPb8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Zr6hyxz1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 23:00:36 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLUq-0001pk-5x; Mon, 27 Apr 2026 08:55:32 -0400", "from eggs.gnu.org ([209.51.188.92])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLSi-0004Ni-Us\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:53:39 -0400", "from mail-wm1-x331.google.com ([2a00:1450:4864:20::331])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNQ-0005V6-Ua\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:54 -0400", "by mail-wm1-x331.google.com with SMTP id\n 5b1f17b1804b1-4891c0620bcso69164705e9.1\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:52 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x331.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nIt enables emulation of ENET ethernet controller in iMX8MM\nEnables testing and debugging of network dependent drivers\nAdded ENET MAC IRQ lines\n\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 24 ++++++++++++++++++++++++\n hw/arm/imx8mm-evk.c | 1 +\n include/hw/arm/fsl-imx8mm.h | 10 +++++++++-\n 4 files changed, 35 insertions(+), 1 deletion(-)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 44dd401c8a..104954d90d 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -625,6 +625,7 @@ config FSL_IMX8MM\n select FSL_IMX8MP_ANALOG\n select FSL_IMX8MP_CCM\n select IMX\n+ select IMX_FEC\n select IMX_I2C\n select OR_IRQ\n select SDHCI\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 3736191257..f1c173dbec 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -212,6 +212,8 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);\n }\n \n+ object_initialize_child(obj, \"eth0\", &s->enet, TYPE_IMX_ENET);\n+\n object_initialize_child(obj, \"pcie\", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);\n object_initialize_child(obj, \"pcie_phy\", &s->pcie_phy,\n TYPE_FSL_IMX8M_PCIE_PHY);\n@@ -547,6 +549,21 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n qdev_get_gpio_in(gicdev, spi_table[i].irq));\n }\n \n+ /* ENET1 */\n+ object_property_set_uint(OBJECT(&s->enet), \"phy-num\", s->phy_num,\n+ &error_abort);\n+ object_property_set_uint(OBJECT(&s->enet), \"tx-ring-num\", 3, &error_abort);\n+ qemu_configure_nic_device(DEVICE(&s->enet), true, NULL);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_ENET1].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_ENET1_MAC_IRQ));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1,\n+ qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IRQ));\n+\n /* SNVS */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {\n return;\n@@ -610,6 +627,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n case FSL_IMX8MM_GPT1 ... FSL_IMX8MM_GPT6:\n case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:\n+ case FSL_IMX8MM_ENET1:\n case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\n@@ -631,10 +649,16 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n }\n }\n \n+static const Property fsl_imx8mm_properties[] = {\n+ DEFINE_PROP_UINT32(\"fec1-phy-num\", FslImx8mmState, phy_num, 0),\n+ DEFINE_PROP_BOOL(\"fec1-phy-connected\", FslImx8mmState, phy_connected, true),\n+};\n+\n static void fsl_imx8mm_class_init(ObjectClass *oc, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(oc);\n \n+ device_class_set_props(dc, fsl_imx8mm_properties);\n dc->realize = fsl_imx8mm_realize;\n \n dc->desc = \"i.MX 8MM SoC\";\ndiff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c\nindex dfdf3cd4f8..6b7774d3e2 100644\n--- a/hw/arm/imx8mm-evk.c\n+++ b/hw/arm/imx8mm-evk.c\n@@ -79,6 +79,7 @@ static void imx8mm_evk_init(MachineState *machine)\n \n s = FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine),\n \"soc\", &error_fatal, NULL));\n+ object_property_set_uint(OBJECT(s), \"fec1-phy-num\", 1, &error_fatal);\n sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);\n \n memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START,\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 607ac86666..bc5a0922ad 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -18,7 +18,8 @@\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n-#include \"hw/or-irq.h\"\n+#include \"hw/net/imx_fec.h\"\n+#include \"hw/core/or-irq.h\"\n #include \"hw/pci-host/designware.h\"\n #include \"hw/pci-host/fsl_imx8m_phy.h\"\n #include \"hw/sd/sdhci.h\"\n@@ -60,11 +61,15 @@ struct FslImx8mmState {\n IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n+ IMXFECState enet;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n OrIRQState gpt5_gpt6_irq;\n+\n+ uint32_t phy_num;\n+ bool phy_connected;\n };\n \n enum FslImx8mmMemoryRegions {\n@@ -218,6 +223,9 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_WDOG2_IRQ = 79,\n FSL_IMX8MM_WDOG3_IRQ = 10,\n \n+ FSL_IMX8MM_ENET1_MAC_IRQ = 118,\n+ FSL_IMX6_ENET1_MAC_1588_IRQ = 121,\n+\n FSL_IMX8MM_PCI_INTA_IRQ = 122,\n FSL_IMX8MM_PCI_INTB_IRQ = 123,\n FSL_IMX8MM_PCI_INTC_IRQ = 124,\n", "prefixes": [ "PULL", "14/63" ] }