Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2228874/?format=api
{ "id": 2228874, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228874/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-8-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-8-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:41", "name": "[PULL,07/63] hw/arm/fsl-imx8mm: Adding support for USDHC storage controllers", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "04701abd45a55a473b7e041f972cae75d329fb94", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-8-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228874/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228874/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Y5i4KPpd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Xp0Z5zz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:58:50 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLUZ-0008CB-NT; Mon, 27 Apr 2026 08:55:15 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNO-0007m2-N0\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400", "from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNL-0005TY-2Q\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:50 -0400", "by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-4891c00e7aeso75993055e9.2\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:46 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.47.44\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 27 Apr 2026 05:47:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777294066; x=1777898866; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=A7tGHyLb32WspsEMndxPwKXjqKNvzmk7fqExwgmp0k8=;\n b=Y5i4KPpdksSPPY13Xeu7BO1SIwuoas1QuH+s0Z125YtKfrd1nROprbptmSoYF46OgS\n FKF8LIzpM+2rQdXh3nOXGnpobVzbQvu3YMTeyv+dr1uIgoikhqSDgAjLk2G6k5gA6Un2\n PoAt3Fp01doiRQOBPwPHI9mWAYNn2lXUKKmVxZbrrdylVTCBewkFswbcEgCTwonPRJX/\n XzCFfq5r4Kbpk1l1vxUoaOSLCGJ+Z9ptpQUuEz9D7KY4JAM8rd9l+JebqDllz8GPinj8\n jVUdoV0zKx6LyxHM2dxnzWDqT4b0OLpVl6795Tk8pLwkaH+0G4nu+C5B6KyvqdW8P9Hx\n z0gA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777294066; x=1777898866;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=A7tGHyLb32WspsEMndxPwKXjqKNvzmk7fqExwgmp0k8=;\n b=TuCPs7YBYFXsqFjuofIifbk3xgZlzu6mpcE/0BSvIg6x9bVerqfwk8i7R1Gw7Tw/Ym\n /0UKi3ppcOVjLxf8ayPFDuv/0AnZZu8oLe6NzDw2jtI/c0f9bk1AMdaAWikeyP6ygswZ\n r2P2AymKbTz7PJ+Oix5VbPdXD8FejU4LZ1AVbPnJ7kKzL2wleYmfMrrYO3XAUs3jFaW9\n hExQGmXc7a7noqCusHgj4FY2aeBhkErHwzE8kLOMN/lViq0kHv589r3p93ccYHKvC6Sd\n kirhUQx/H6C5vJus5eY9Xyf1pBji+g5iSMPjmXn3lyfDA3KBE88Kx44zl7+7FRat91St\n OOsA==", "X-Gm-Message-State": "AOJu0Yzsx0fAs0N57AxUK1QoLKBjTY6FYdZ74ZFdkzXnUkLOJwlvYVPN\n PdG/WeWBw4Mr0Nmuy6ZZ6MkKVR93gYaqWzTOopiYb7iCtavt8AUjpU9mlQxpHTairiLBcNNTItD\n j+cd/", "X-Gm-Gg": "AeBDietvKQFYIZ6mV9mCFBTiaMhod61HszXSslXeIikLynwFPt9Qpmoh9GBwUYVJPDq\n DQdAzC1bTTKkTHRBT4ESNdNCk3wcaAKeH5XedAehygM+z8Ysu4z0tPxAEh6dh2s33kuLPiL7ZaC\n DxS+EBAINSCWw7x4BKN//P+c17pHvDWRfGQcaj2mkUnUL0JGNnPNNZedBGu2fk0KeFQGk6+g5/6\n urRj7j1+YrHEwVYw4M6IW6F/tdkQG5ruNGVTzZMrM5diFAez4tjrxjBjnQewjaJBrXNKaV9aMA/\n o5x+Uhy5WU+tuyRBTPF71BrSQquGydukIKaoLdZGlCCPp2nLmOY6p0Esdr7PDlWPNrEJJW6ri7J\n EF4XKmjqZrWVUh5fBAFSiwuoxOV6VratAeOW0ul+GEqL2nTzbeY1QctQaTPwXfEcPvI0hVE/+hb\n Xo03t5QmE9SQNUBx43xTU+gisGfD3ctGRuUOa0wh3bGxcblqJnsgoSZGSeUNQfmAckLLeS8U1xo\n 4ChuAgx5id34NizR5PQT/SK50QXIGmTzhQzh1fS7g==", "X-Received": "by 2002:a05:600c:46cb:b0:488:a723:ea53 with SMTP id\n 5b1f17b1804b1-488fb744fbemr616335055e9.7.1777294065563;\n Mon, 27 Apr 2026 05:47:45 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 07/63] hw/arm/fsl-imx8mm: Adding support for USDHC storage\n controllers", "Date": "Mon, 27 Apr 2026 13:46:41 +0100", "Message-ID": "<20260427124738.966578-8-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427124738.966578-1-peter.maydell@linaro.org>", "References": "<20260427124738.966578-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nIt enables emulation of SD/MMC cards through a virtual SDHCI interface\nThe emulated SDHCI controller allows guest OS to use emulated storage as\na standard block device.\nThis will allow running the images such as those generated\nby Buildroot.\n\nReviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 25 +++++++++++++++++++++++++\n hw/arm/imx8mm-evk.c | 17 +++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 7 +++++++\n 4 files changed, 50 insertions(+)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 26dc3e6ed1..74e8c431a2 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -623,6 +623,7 @@ config FSL_IMX8MM\n select FSL_IMX8MP_ANALOG\n select FSL_IMX8MP_CCM\n select IMX\n+ select SDHCI\n \n config FSL_IMX8MM_EVK\n bool\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 8999bc701e..2a4d4d5e6d 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -180,6 +180,10 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"usdhc%d\", i + 1);\n+ object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n+ }\n }\n \n static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n@@ -357,6 +361,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n \n+ /* USDHCs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } usdhc_table[FSL_IMX8MM_NUM_USDHCS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC1].addr, FSL_IMX8MM_USDHC1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC2].addr, FSL_IMX8MM_USDHC2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC3].addr, FSL_IMX8MM_USDHC3_IRQ },\n+ };\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,\n+ qdev_get_gpio_in(gicdev, usdhc_table[i].irq));\n+ }\n+\n /* SNVS */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {\n return;\n@@ -375,6 +399,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_OCRAM:\n case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n+ case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:\n /* device implemented and treated above */\n break;\n \ndiff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c\nindex 0a8cce8866..dfdf3cd4f8 100644\n--- a/hw/arm/imx8mm-evk.c\n+++ b/hw/arm/imx8mm-evk.c\n@@ -84,6 +84,23 @@ static void imx8mm_evk_init(MachineState *machine)\n memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START,\n machine->ram);\n \n+ for (int i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n+ BusState *bus;\n+ DeviceState *carddev;\n+ BlockBackend *blk;\n+ DriveInfo *di = drive_get(IF_SD, i, 0);\n+\n+ if (!di) {\n+ continue;\n+ }\n+\n+ blk = blk_by_legacy_dinfo(di);\n+ bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), \"sd-bus\");\n+ carddev = qdev_new(TYPE_SD_CARD);\n+ qdev_prop_set_drive_err(carddev, \"drive\", blk, &error_fatal);\n+ qdev_realize_and_unref(carddev, bus, &error_fatal);\n+ }\n+\n if (!qtest_enabled()) {\n arm_load_kernel(&s->cpu[0], machine, &boot_info);\n }\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 8a172b89e0..93a30a2f55 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -16,6 +16,7 @@\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n+#include \"hw/sd/sdhci.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -29,6 +30,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n+ FSL_IMX8MM_NUM_USDHCS = 3,\n };\n \n struct FslImx8mmState {\n@@ -41,6 +43,7 @@ struct FslImx8mmState {\n IMX7SNVSState snvs;\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n+ SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n };\n \n enum FslImx8mmMemoryRegions {\n@@ -155,6 +158,10 @@ enum FslImx8mmMemoryRegions {\n };\n \n enum FslImx8mmIrqs {\n+ FSL_IMX8MM_USDHC1_IRQ = 22,\n+ FSL_IMX8MM_USDHC2_IRQ = 23,\n+ FSL_IMX8MM_USDHC3_IRQ = 24,\n+\n FSL_IMX8MM_UART1_IRQ = 26,\n FSL_IMX8MM_UART2_IRQ = 27,\n FSL_IMX8MM_UART3_IRQ = 28,\n", "prefixes": [ "PULL", "07/63" ] }