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GET /api/1.1/patches/2228866/?format=api
{ "id": 2228866, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228866/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-32-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-32-peter.maydell@linaro.org>", "date": "2026-04-27T12:47:05", "name": "[PULL,31/63] target/arm/cpu: Introduce the infrastructure for cpreg migration tolerances", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "52671d83d4d7465419a497a830628ee45f482192", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-32-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228866/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228866/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=AQFuz+Sm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43WQ20Qlz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:57:38 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLQy-0002hg-Sr; Mon, 27 Apr 2026 08:51:33 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNq-00084j-9w\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:25 -0400", "from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNi-0005fy-Q3\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:13 -0400", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-488e1a8ac40so126645365e9.2\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:48:09 -0700 (PDT)", "from lanath.. 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The tolerance applies to a given cpreg kvm index,\nand can be of different types:\na) mismatch in cpreg indexes\n- ToleranceNotOnBothEnds (cpreg index is allowed to be only present\n on one end)\n- ToleranceOnlySrcTestValue (cpreg index is allowed to be only\n present in source if its value @mask field matches @value)\nb) mismatch in cpreg values\n- ToleranceDiffInMask (value differences are allowed only within a mask)\n- ToleranceFieldLT (incoming field value must be less than a given value)\n- ToleranceFieldGT (incoming field value must be greater than a given value)\n\nA QLIST of such tolerances can be populated using a new helper:\narm_register_cpreg_mig_tolerance() and arm_cpu_match_cpreg_mig_tolerance()\nallows to check whether a tolerance exists for a given kvm index and its\ncriterion is matched.\n\ncallers for those helpers will be introduced in subsequent patches.\n\nOnly registration of migration tolerances related to cpreg index\nmismatch is currently allowed.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nMessage-id: 20260420140552.104369-2-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu.c | 82 ++++++++++++++++++++++++++++++++++++++++++\n target/arm/cpu.h | 1 +\n target/arm/internals.h | 54 ++++++++++++++++++++++++++++\n 3 files changed, 137 insertions(+)", "diff": "diff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 9b80dda140..10feb639c4 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -181,6 +181,82 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,\n QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);\n }\n \n+static ARMCPRegMigTolerance *find_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx)\n+{\n+ ARMCPRegMigTolerance *t;\n+ QLIST_FOREACH(t, &cpu->cpreg_mig_tolerances, node) {\n+ if (t->kvmidx == kvmidx) {\n+ return t;\n+ }\n+ }\n+ return NULL;\n+}\n+\n+void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx,\n+ uint64_t mask, uint64_t value,\n+ ARMCPRegMigToleranceType type)\n+{\n+ ARMCPRegMigTolerance *entry;\n+\n+ /* make sure the kvmidx has not tolerance already registered */\n+ assert(!find_mig_tolerance(cpu, kvmidx));\n+\n+ assert(type == ToleranceNotOnBothEnds ||\n+ type == ToleranceOnlySrcTestValue);\n+\n+ entry = g_new0(ARMCPRegMigTolerance, 1);\n+\n+ entry->kvmidx = kvmidx;\n+ entry->mask = mask;\n+ entry->value = value;\n+ entry->type = type;\n+\n+ QLIST_INSERT_HEAD(&cpu->cpreg_mig_tolerances, entry, node);\n+}\n+\n+bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx,\n+ uint64_t vmstate_value, uint64_t local_value,\n+ ARMCPRegMigToleranceType type)\n+{\n+ ARMCPRegMigTolerance *t = find_mig_tolerance(cpu, kvmidx);\n+ uint64_t diff, diff_outside_mask, field;\n+\n+ if (!t || t->type != type) {\n+ return false;\n+ }\n+\n+ if (type == ToleranceNotOnBothEnds) {\n+ return true;\n+ }\n+\n+ if (type == ToleranceOnlySrcTestValue &&\n+ ((vmstate_value & t->mask) == t->value)) {\n+ return true;\n+ }\n+\n+ /* Need to check the mask */\n+ diff = vmstate_value ^ local_value;\n+ diff_outside_mask = diff & ~t->mask;\n+\n+ if (diff_outside_mask) {\n+ /* there are differences outside of the mask */\n+ return false;\n+ }\n+ if (type == ToleranceDiffInMask) {\n+ /* differences only in the field, tolerance matched */\n+ return true;\n+ }\n+ /* need to compare field value against authorized ones */\n+ field = vmstate_value & t->mask;\n+ if (type == ToleranceFieldLT && (field < t->value)) {\n+ return true;\n+ }\n+ if (type == ToleranceFieldGT && (field > t->value)) {\n+ return true;\n+ }\n+ return false;\n+}\n+\n static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)\n {\n /* Reset a single ARMCPRegInfo register */\n@@ -1102,6 +1178,7 @@ static void arm_cpu_initfn(Object *obj)\n \n QLIST_INIT(&cpu->pre_el_change_hooks);\n QLIST_INIT(&cpu->el_change_hooks);\n+ QLIST_INIT(&cpu->cpreg_mig_tolerances);\n \n #ifdef CONFIG_USER_ONLY\n # ifdef TARGET_AARCH64\n@@ -1574,6 +1651,7 @@ static void arm_cpu_finalizefn(Object *obj)\n {\n ARMCPU *cpu = ARM_CPU(obj);\n ARMELChangeHook *hook, *next;\n+ ARMCPRegMigTolerance *t, *n;\n \n g_hash_table_destroy(cpu->cp_regs);\n \n@@ -1585,6 +1663,10 @@ static void arm_cpu_finalizefn(Object *obj)\n QLIST_REMOVE(hook, node);\n g_free(hook);\n }\n+ QLIST_FOREACH_SAFE(t, &cpu->cpreg_mig_tolerances, node, n) {\n+ QLIST_REMOVE(t, node);\n+ g_free(t);\n+ }\n #ifndef CONFIG_USER_ONLY\n if (cpu->pmu_timer) {\n timer_free(cpu->pmu_timer);\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex ab6bacf4aa..be14a47c35 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1140,6 +1140,7 @@ struct ArchCPU {\n \n QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;\n QLIST_HEAD(, ARMELChangeHook) el_change_hooks;\n+ QLIST_HEAD(, ARMCPRegMigTolerance) cpreg_mig_tolerances;\n \n int32_t node_id; /* NUMA node this CPU belongs to */\n \ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 06655409e5..a632584a4e 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1943,4 +1943,58 @@ int compare_u64(const void *a, const void *b);\n /* Used in FEAT_MEC to set the MECIDWidthm1 field in the MECIDR_EL2 register. */\n #define MECID_WIDTH 16\n \n+typedef enum {\n+ ToleranceNotOnBothEnds,\n+ ToleranceOnlySrcTestValue,\n+ ToleranceDiffInMask,\n+ ToleranceFieldLT,\n+ ToleranceFieldGT,\n+} ARMCPRegMigToleranceType;\n+\n+typedef struct ARMCPRegMigTolerance {\n+ uint64_t kvmidx;\n+ uint64_t mask;\n+ uint64_t value;\n+ ARMCPRegMigToleranceType type;\n+ QLIST_ENTRY(ARMCPRegMigTolerance) node;\n+} ARMCPRegMigTolerance;\n+\n+/**\n+ * arm_register_cpreg_mig_tolerance:\n+ * Register a migration tolerance wrt one given cpreg identified by its\n+ * @kvmidx. Calling this function twice for the same @kvmidx is a\n+ * programming error and will cause an assertion failure.\n+ *\n+ * @cpu: vcpu to apply the migration tolerance on\n+ * @kvmidx: kvm index of the cpreg the tolerance applies to\n+ * @mask: bitmask where a difference is tolerated\n+ * (relevant with ToleranceDiffInMask)\n+ * @value: value the bitmask field is compared with\n+ * (relevant with ToleranceFieldLT and ToleranceFieldGT)\n+ * @type: type of the migration tolerance:\n+ * - ToleranceNotOnBothEnds (cpreg index is allowed to be only present\n+ * on one end)\n+ * - ToleranceOnlySrcTestValue (cpreg index is allowed to be only\n+ * present in source if its value @mask field matches @value)\n+ * - ToleranceDiffInMask (mismatch in cpreg values are only tolerated\n+ * if differences are within @mask)\n+ * - ToleranceFieldLT (mismatch in cpreg values are only tolerated\n+ * if incoming @bitmask field value is less than @value)\n+ * - ToleranceFieldGT (mismatch in cpreg values are only tolerated\n+ * if incoming @bitmask field value is greater than @value)\n+ */\n+void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx,\n+ uint64_t mask, uint64_t value,\n+ ARMCPRegMigToleranceType type);\n+\n+/**\n+ * arm_cpu_match_cpreg_mig_tolerance:\n+ * Check whether a tolerance of type @type exists for a given @kvmidx\n+ * and the tolerance criterion is satisfied\n+ */\n+bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx,\n+ uint64_t vmstate_value, uint64_t local_value,\n+ ARMCPRegMigToleranceType type);\n+\n+\n #endif\n", "prefixes": [ "PULL", "31/63" ] }