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GET /api/1.1/patches/2228863/?format=api
{ "id": 2228863, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228863/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-51-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-51-peter.maydell@linaro.org>", "date": "2026-04-27T12:47:24", "name": "[PULL,50/63] target/arm: migrate fault syndromes to registerfields", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "e0389f1c3b0ddb7b98bb95311946f799fe56b2e4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-51-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228863/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228863/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fIsXU42M;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43WF6Xy2z1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:57:29 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLR0-0002wo-O3; Mon, 27 Apr 2026 08:51:34 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLO6-0008CA-Iz\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400", "from mail-wm1-x334.google.com ([2a00:1450:4864:20::334])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLO1-0005kb-OS\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:33 -0400", "by mail-wm1-x334.google.com with SMTP id\n 5b1f17b1804b1-483487335c2so99996955e9.2\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:48:26 -0700 (PDT)", "from lanath.. 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"<20260427124738.966578-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::334;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Alex Bennée <alex.bennee@linaro.org>\n\nMigrate syn_insn_abort and syn_data_abort_* to the registerfields API.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nTested-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-id: 20260422125250.1303100-11-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/syndrome.h | 87 ++++++++++++++++++++++++++++++++++++-------\n 1 file changed, 74 insertions(+), 13 deletions(-)", "diff": "diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex bc65106c61..2031b3704f 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -494,20 +494,64 @@ static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr,\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an Instruction Abort\n+ *\n+ * (aka instruction abort)\n+ */\n+FIELD(IABORT_ISS, IFSC, 0, 6)\n+FIELD(IABORT_ISS, S1PTW, 7, 1)\n+FIELD(IABORT_ISS, EA, 9, 1)\n+FIELD(IABORT_ISS, FnV, 10, 1) /* FAR not Valid */\n+FIELD(IABORT_ISS, SET, 11, 2)\n+FIELD(IABORT_ISS, PFV, 14, 1)\n+FIELD(IABORT_ISS, TopLevel, 21, 1) /* FEAT_THE */\n+\n static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)\n {\n- return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_INSNABORT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, IABORT_ISS, EA, ea);\n+ res = FIELD_DP32(res, IABORT_ISS, S1PTW, s1ptw);\n+ res = FIELD_DP32(res, IABORT_ISS, IFSC, fsc);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from a Data Abort\n+ */\n+FIELD(DABORT_ISS, DFSC, 0, 6)\n+FIELD(DABORT_ISS, WNR, 6, 1)\n+FIELD(DABORT_ISS, S1PTW, 7, 1)\n+FIELD(DABORT_ISS, CM, 8, 1)\n+FIELD(DABORT_ISS, EA, 9, 1)\n+FIELD(DABORT_ISS, FnV, 10, 1)\n+FIELD(DABORT_ISS, LST, 11, 2)\n+FIELD(DABORT_ISS, VNCR, 13, 1)\n+FIELD(DABORT_ISS, AR, 14, 1)\n+FIELD(DABORT_ISS, SF, 15, 1)\n+FIELD(DABORT_ISS, SRT, 16, 5)\n+FIELD(DABORT_ISS, SSE, 21, 1)\n+FIELD(DABORT_ISS, SAS, 22, 2)\n+FIELD(DABORT_ISS, ISV, 24, 1)\n+\n static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv,\n int ea, int cm, int s1ptw,\n int wnr, int fsc)\n {\n- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL\n- | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7)\n- | (wnr << 6) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_DATAABORT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, DABORT_ISS, FnV, fnv);\n+ res = FIELD_DP32(res, DABORT_ISS, EA, ea);\n+ res = FIELD_DP32(res, DABORT_ISS, CM, cm);\n+ res = FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw);\n+ res = FIELD_DP32(res, DABORT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, DABORT_ISS, DFSC, fsc);\n+\n+ return res;\n }\n \n static inline uint32_t syn_data_abort_with_iss(int same_el,\n@@ -517,11 +561,22 @@ static inline uint32_t syn_data_abort_with_iss(int same_el,\n int wnr, int fsc,\n bool is_16bit)\n {\n- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)\n- | (sf << 15) | (ar << 14)\n- | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_DATAABORT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, DABORT_ISS, ISV, 1);\n+ res = FIELD_DP32(res, DABORT_ISS, SAS, sas);\n+ res = FIELD_DP32(res, DABORT_ISS, SSE, sse);\n+ res = FIELD_DP32(res, DABORT_ISS, SRT, srt);\n+ res = FIELD_DP32(res, DABORT_ISS, SF, sf);\n+ res = FIELD_DP32(res, DABORT_ISS, AR, ar);\n+ res = FIELD_DP32(res, DABORT_ISS, EA, ea);\n+ res = FIELD_DP32(res, DABORT_ISS, CM, cm);\n+ res = FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw);\n+ res = FIELD_DP32(res, DABORT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, DABORT_ISS, DFSC, fsc);\n+\n+ return res;\n }\n \n /*\n@@ -530,8 +585,14 @@ static inline uint32_t syn_data_abort_with_iss(int same_el,\n */\n static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc)\n {\n- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_DATAABORT_SAME_EL);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, DABORT_ISS, VNCR, 1);\n+ res = FIELD_DP32(res, DABORT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, DABORT_ISS, DFSC, fsc);\n+\n+ return res;\n }\n \n static inline uint32_t syn_swstep(int same_el, int isv, int ex)\n", "prefixes": [ "PULL", "50/63" ] }