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GET /api/1.1/patches/2228843/?format=api
{ "id": 2228843, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228843/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-16-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-16-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:49", "name": "[PULL,15/63] hw/arm/fsl-imx8mm: Adding support for USB controller", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "9c2a34db32f04ab13c6921b207cd3c5798987f90", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-16-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228843/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228843/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Gfbni2pn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43T074sBz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:55:32 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLOv-0000jS-MV; Mon, 27 Apr 2026 08:49:27 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNa-0007tW-Mb\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:12 -0400", "from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNR-0005VG-VV\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:00 -0400", "by mail-wm1-x32d.google.com with SMTP id\n 5b1f17b1804b1-48a3e9862f0so54014845e9.1\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:53 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nIt enables emulation of USB on iMX8MM\nEnables testing and debugging of USB drivers\n\nReviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 27 +++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 6 ++++++\n 3 files changed, 34 insertions(+)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 104954d90d..b940af9345 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -631,6 +631,7 @@ config FSL_IMX8MM\n select SDHCI\n select PCI_EXPRESS_DESIGNWARE\n select PCI_EXPRESS_FSL_IMX8M_PHY\n+ select USB_DWC3\n select WDT_IMX2\n \n config FSL_IMX8MM_EVK\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex f1c173dbec..97c3f8542c 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -202,6 +202,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_USBS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"usb%d\", i);\n+ object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3);\n+ }\n+\n for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {\n g_autofree char *name = g_strdup_printf(\"spi%d\", i + 1);\n object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);\n@@ -529,6 +534,27 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n qdev_get_gpio_in(gicdev, usdhc_table[i].irq));\n }\n \n+ /* USBs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_USBS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } usb_table[FSL_IMX8MM_NUM_USBS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USB1].addr, FSL_IMX8MM_USB1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USB2].addr, FSL_IMX8MM_USB2_IRQ },\n+ };\n+\n+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), \"p2\", 1);\n+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), \"p3\", 1);\n+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), \"slots\", 2);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,\n+ qdev_get_gpio_in(gicdev, usb_table[i].irq));\n+ }\n+\n /* ECSPIs */\n for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {\n static const struct {\n@@ -635,6 +661,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_OCRAM:\n case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n+ case FSL_IMX8MM_USB1 ... FSL_IMX8MM_USB2:\n case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:\n case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3:\n /* device implemented and treated above */\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex bc5a0922ad..60d79a6e3c 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -25,6 +25,7 @@\n #include \"hw/sd/sdhci.h\"\n #include \"hw/ssi/imx_spi.h\"\n #include \"hw/timer/imx_gpt.h\"\n+#include \"hw/usb/hcd-dwc3.h\"\n #include \"hw/watchdog/wdt_imx2.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n@@ -43,6 +44,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_I2CS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n+ FSL_IMX8MM_NUM_USBS = 2,\n FSL_IMX8MM_NUM_USDHCS = 3,\n FSL_IMX8MM_NUM_WDTS = 3,\n };\n@@ -64,6 +66,7 @@ struct FslImx8mmState {\n IMXFECState enet;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n+ USBDWC3 usb[FSL_IMX8MM_NUM_USBS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n OrIRQState gpt5_gpt6_irq;\n@@ -202,6 +205,9 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_I2C3_IRQ = 37,\n FSL_IMX8MM_I2C4_IRQ = 38,\n \n+ FSL_IMX8MM_USB1_IRQ = 40,\n+ FSL_IMX8MM_USB2_IRQ = 41,\n+\n FSL_IMX8MM_GPT1_IRQ = 55,\n FSL_IMX8MM_GPT2_IRQ = 54,\n FSL_IMX8MM_GPT3_IRQ = 53,\n", "prefixes": [ "PULL", "15/63" ] }