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GET /api/1.1/patches/2228826/?format=api
{ "id": 2228826, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228826/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-6-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-6-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:39", "name": "[PULL,05/63] hw/arm/fsl-imx8mm: Add Clock Control Module IP to iMX8MM", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "cadbf6e0ae993693a554b122330a1682ede23a01", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-6-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228826/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228826/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=FrtjvHHe;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43NV1v5Vz23Zb\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:51:38 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLOp-0000Uo-43; Mon, 27 Apr 2026 08:49:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNN-0007lR-4k\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400", "from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNK-0005Sg-Nh\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:48 -0400", "by mail-wm1-x32c.google.com with SMTP id\n 5b1f17b1804b1-488e1a8ac40so126639755e9.2\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:44 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nAdd the Clock Control Module (CCM) device to i.MX8MM SoC.\nThe CCM implementation is shared with i.MX8MP as the register\nlayout is identical between the two variants.Hence iMX8MM will\nbe using the source of iMX8MP CCM.\n\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 10 ++++++++++\n include/hw/arm/fsl-imx8mm.h | 2 ++\n 3 files changed, 13 insertions(+)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex b3db2d6848..26dc3e6ed1 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -621,6 +621,7 @@ config FSL_IMX8MM\n bool\n select ARM_GIC\n select FSL_IMX8MP_ANALOG\n+ select FSL_IMX8MP_CCM\n select IMX\n \n config FSL_IMX8MM_EVK\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 8218448074..053434412c 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -169,6 +169,8 @@ static void fsl_imx8mm_init(Object *obj)\n \n object_initialize_child(obj, \"gic\", &s->gic, gicv3_class_name());\n \n+ object_initialize_child(obj, \"ccm\", &s->ccm, TYPE_IMX8MP_CCM);\n+\n object_initialize_child(obj, \"analog\", &s->analog, TYPE_IMX8MP_ANALOG);\n \n for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n@@ -305,6 +307,13 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n }\n }\n \n+ /* CCM */\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_CCM].addr);\n+\n /* Analog */\n object_property_set_uint(OBJECT(&s->analog), \"arm-pll-fdiv-ctl0-reset\",\n 0x000fa030, &error_abort);\n@@ -350,6 +359,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {\n switch (i) {\n case FSL_IMX8MM_ANA_PLL:\n+ case FSL_IMX8MM_CCM:\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_RAM:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 0a020c32a1..df35f0f5ac 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -14,6 +14,7 @@\n #include \"hw/char/imx_serial.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n+#include \"hw/misc/imx8mp_ccm.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -34,6 +35,7 @@ struct FslImx8mmState {\n \n ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n GICv3State gic;\n+ IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n", "prefixes": [ "PULL", "05/63" ] }