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GET /api/1.1/patches/2228825/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2228825,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228825/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-44-peter.maydell@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260427124738.966578-44-peter.maydell@linaro.org>",
    "date": "2026-04-27T12:47:17",
    "name": "[PULL,43/63] target/arm: migrate FP/SIMD trap syndromes to registerfields",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": false,
    "hash": "eb100e619f882b852a9a7e30e4a3b0106bdaca3b",
    "submitter": {
        "id": 5111,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api",
        "name": "Peter Maydell",
        "email": "peter.maydell@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-44-peter.maydell@linaro.org/mbox/",
    "series": [
        {
            "id": 501642,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642",
            "date": "2026-04-27T12:46:34",
            "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2228825/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2228825/checks/",
    "tags": {},
    "headers": {
        "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>",
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        "From": "Peter Maydell <peter.maydell@linaro.org>",
        "To": "qemu-devel@nongnu.org",
        "Subject": "[PULL 43/63] target/arm: migrate FP/SIMD trap syndromes to\n registerfields",
        "Date": "Mon, 27 Apr 2026 13:47:17 +0100",
        "Message-ID": "<20260427124738.966578-44-peter.maydell@linaro.org>",
        "X-Mailer": "git-send-email 2.43.0",
        "In-Reply-To": "<20260427124738.966578-1-peter.maydell@linaro.org>",
        "References": "<20260427124738.966578-1-peter.maydell@linaro.org>",
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    },
    "content": "From: Alex Bennée <alex.bennee@linaro.org>\n\nThe syn_simd_access trap was never used so remove it. We should only\nsee the COPROC encoding on v7 architectures.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-id: 20260422125250.1303100-4-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/syndrome.h | 25 +++++++++++++++----------\n 1 file changed, 15 insertions(+), 10 deletions(-)",
    "diff": "diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 29462aa103..72051443d5 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -337,21 +337,26 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,\n     return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an access to a register of\n+ * instruction resulting from the FPEN or TFP traps.\n+ */\n+FIELD(FP_ISS, COPROC, 0, 4) /* ARMv7 only */\n+FIELD(FP_ISS, COND, 20, 4)\n+FIELD(FP_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,\n                                           int coproc)\n {\n     /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */\n-    return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)\n-        | (is_16bit ? 0 : ARM_EL_IL)\n-        | (cv << 24) | (cond << 20) | coproc;\n-}\n+    uint32_t res = syn_set_ec(0, EC_ADVSIMDFPACCESSTRAP);\n+    res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n \n-static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)\n-{\n-    /* AArch32 SIMD trap: TA == 1 coproc == 0 */\n-    return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)\n-        | (is_16bit ? 0 : ARM_EL_IL)\n-        | (cv << 24) | (cond << 20) | (1 << 5);\n+    res = FIELD_DP32(res, FP_ISS, CV, cv);\n+    res = FIELD_DP32(res, FP_ISS, COND, cond);\n+    res = FIELD_DP32(res, FP_ISS, COPROC, coproc);\n+\n+    return res;\n }\n \n static inline uint32_t syn_sve_access_trap(void)\n",
    "prefixes": [
        "PULL",
        "43/63"
    ]
}