Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2228820/?format=api
{ "id": 2228820, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228820/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-10-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-10-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:43", "name": "[PULL,09/63] hw/arm/fsl-imx8mm: Add GPIO controllers", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "4ce980159b3178b9015ab5fd25e0ebae5a18d044", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-10-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228820/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228820/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fstvomou;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43MV6zzPz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:50:46 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLP7-0000qo-AA; Mon, 27 Apr 2026 08:49:41 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNP-0007nS-TO\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400", "from mail-wm1-x336.google.com ([2a00:1450:4864:20::336])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNM-0005Tw-S1\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400", "by mail-wm1-x336.google.com with SMTP id\n 5b1f17b1804b1-488b8bc6bc9so73659755e9.3\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:48 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.47.46\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 27 Apr 2026 05:47:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777294067; x=1777898867; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=fbBhWQytfoalSexEb/LcbiWO60wmmMN2iBOzllNIQM8=;\n b=fstvomouKDHmK7GY9blQzWwmBiNkDJjHHc2a1CgNwKIGwhsDCQRJjelwZ9uI8Sm10o\n NJaMfePV/JkpyMgahJecUB7m2XPjlE9EiAlFcrKI9WY4JDq9NuCKSldnosoOY6K41nZ+\n fgjY87fCA2UagAE6HMsudi/SPJLE4Ys4aITOwTIdooR/0DCWJzPjugz8w7aG/x4XeU5P\n 5d4L6wl1yCxx+A4xfjXMKPs900e3yLBEm/j6NO6Zh760HJCEYPI3VrNet2ffVAbdyDHe\n P4L2ObiFwIlyplQmGodyVVw+fbHq3gxDTDJ1CFR1fGG/yB96TCl4W8AMEO8Dxpbq/Xew\n kd4A==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777294067; x=1777898867;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=fbBhWQytfoalSexEb/LcbiWO60wmmMN2iBOzllNIQM8=;\n b=awSykLSKvNYumpAbqifBXHuJTbYX+T+b3z1qMtyPbrCXmXVMvFg7lrjIeV7xSgh6MD\n CWnfBwzZ6EX5GxjhuxkM2a1hK+/zZtlp62VaQoMRYfLx7Hn1yElwhbDsxtkVbN1pJOPi\n bR1jpDksJPs97Dk8c3fbdikjOyiozS2/1kk8tyV/x9gx/qfRRldHx1ILTUoaYXmjFhaA\n cW+n4vxcauhKCJuTw48nYNwGAzkBiBMSgVBxG6qpk9KpmfSz8Cqs+k8stNJbRrg++58v\n fU1BV1bkNaykEKtWWBuM/ThlS5T7naZI33CzKUfoM0vhbdPAyKjXFuT22ZDbdS1Xsr5k\n GIfA==", "X-Gm-Message-State": "AOJu0YwMxFVM62jLWSbKHZfPpe41XNBQhTf+50lxBOQipk4IzfpHQML3\n 7m9+fpe0lWlQy4g0Ildqrl9zln9eYFkyPltS6wFEalhedNY2zjxcCWzrRcS8TVPs6z6hnBnqALs\n BGZlJ", "X-Gm-Gg": "AeBDieuCnuiQOc3XtGUi58SgX8gvqoA19xlmmmCtvDgMeng0hMIpOMFhybFdqv46m4X\n mKIhjDVwU1tBNR2L9FkfaIHVzb5xyPhFSWfxwBBhfT+tRQ1BoObepvVcbgu0stDetEgqibGrBWr\n cxPtk9GB1Q2KzVIo8cgvBoI7QhJ4kHoIQ0IY5rklpaOP5WSl+7mDE8ObMQxWmYislfhayiXz9b1\n t8UcmuT5kbjSy1gdrzGaf+FTUQ4o21Jp4xnsPdBBbQENx9/MC+bVaF9gx9MVFfI3E0t/L1FjMaT\n BDrCV9h6JTUSVJ8VQEa4X4v/bCPtShd/4mcETNIivE2F7d5zU8tHzIjmeziEYUcuKhtYWjV5C+A\n OsiKE1vcPe44hqn0pMvpY2ZydVyO5dCNIr3tX6HuX1jxDdTXQF0H8lYpcQIrGWKMIwfMP78qItO\n GSrzkGKkLdXDZ6tkTCFvT/5a2vx8cYjp7zglJWasCkLLMvzHxNk9huSO4NXpFsJpVrLbyUjHkEO\n QBMDRGJjFbYrgfVvVmIevrP6yEy5IT9LbbWpJ+V6Q==", "X-Received": "by 2002:a05:600c:3b14:b0:48a:52d9:54ab with SMTP id\n 5b1f17b1804b1-48a52d95604mr449733475e9.30.1777294067124;\n Mon, 27 Apr 2026 05:47:47 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 09/63] hw/arm/fsl-imx8mm: Add GPIO controllers", "Date": "Mon, 27 Apr 2026 13:46:43 +0100", "Message-ID": "<20260427124738.966578-10-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427124738.966578-1-peter.maydell@linaro.org>", "References": "<20260427124738.966578-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::336;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nEnabled GPIO controller emulation\nAlso updated the GPIO IRQ lines of iMX8MM\n\nReviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/fsl-imx8mm.c | 54 +++++++++++++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 14 ++++++++++\n 2 files changed, 68 insertions(+)", "diff": "diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 633b121630..85bce5a788 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"gpio%d\", i + 1);\n+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);\n+ }\n+\n for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n g_autofree char *name = g_strdup_printf(\"usdhc%d\", i + 1);\n object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n@@ -365,6 +370,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n \n+ /* GPIOs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq_low;\n+ unsigned int irq_high;\n+ } gpio_table[FSL_IMX8MM_NUM_GPIOS] = {\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr,\n+ FSL_IMX8MM_GPIO1_LOW_IRQ,\n+ FSL_IMX8MM_GPIO1_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr,\n+ FSL_IMX8MM_GPIO2_LOW_IRQ,\n+ FSL_IMX8MM_GPIO2_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr,\n+ FSL_IMX8MM_GPIO3_LOW_IRQ,\n+ FSL_IMX8MM_GPIO3_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr,\n+ FSL_IMX8MM_GPIO4_LOW_IRQ,\n+ FSL_IMX8MM_GPIO4_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr,\n+ FSL_IMX8MM_GPIO5_LOW_IRQ,\n+ FSL_IMX8MM_GPIO5_HIGH_IRQ\n+ },\n+ };\n+ object_property_set_bool(OBJECT(&s->gpio[i]), \"has-edge-sel\", true,\n+ &error_abort);\n+ object_property_set_bool(OBJECT(&s->gpio[i]), \"has-upper-pin-irq\",\n+ true, &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,\n+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,\n+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));\n+ }\n+\n /* USDHCs */\n for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n static const struct {\n@@ -423,6 +476,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_CCM:\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n+ case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\n case FSL_IMX8MM_RAM:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 3181c02574..4fe27b9575 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -12,6 +12,7 @@\n \n #include \"cpu.h\"\n #include \"hw/char/imx_serial.h\"\n+#include \"hw/gpio/imx_gpio.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n@@ -30,6 +31,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)\n \n enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n+ FSL_IMX8MM_NUM_GPIOS = 5,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n FSL_IMX8MM_NUM_USDHCS = 3,\n@@ -40,6 +42,7 @@ struct FslImx8mmState {\n \n ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n GICv3State gic;\n+ IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];\n IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n IMX7SNVSState snvs;\n@@ -171,6 +174,17 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_UART3_IRQ = 28,\n FSL_IMX8MM_UART4_IRQ = 29,\n \n+ FSL_IMX8MM_GPIO1_LOW_IRQ = 64,\n+ FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,\n+ FSL_IMX8MM_GPIO2_LOW_IRQ = 66,\n+ FSL_IMX8MM_GPIO2_HIGH_IRQ = 67,\n+ FSL_IMX8MM_GPIO3_LOW_IRQ = 68,\n+ FSL_IMX8MM_GPIO3_HIGH_IRQ = 69,\n+ FSL_IMX8MM_GPIO4_LOW_IRQ = 70,\n+ FSL_IMX8MM_GPIO4_HIGH_IRQ = 71,\n+ FSL_IMX8MM_GPIO5_LOW_IRQ = 72,\n+ FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,\n+\n FSL_IMX8MM_PCI_INTA_IRQ = 122,\n FSL_IMX8MM_PCI_INTB_IRQ = 123,\n FSL_IMX8MM_PCI_INTC_IRQ = 124,\n", "prefixes": [ "PULL", "09/63" ] }