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GET /api/1.1/patches/2228819/?format=api
{ "id": 2228819, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228819/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-9-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-9-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:42", "name": "[PULL,08/63] hw/arm/fsl-imx8mm: Add PCIe support", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "467703fe96baa0ce96e47ab2e9251175b2ba2eef", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-9-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228819/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228819/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HUwYVXlz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43MF5Jv7z1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:50:33 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLP4-0000qZ-5f; Mon, 27 Apr 2026 08:49:37 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNP-0007nT-Tk\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400", "from mail-wm1-x334.google.com ([2a00:1450:4864:20::334])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNM-0005Te-LH\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400", "by mail-wm1-x334.google.com with SMTP id\n 5b1f17b1804b1-4891e5b9c1fso86366965e9.2\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:47 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x334.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nThis enables support for Designware PCI Express Controller emulation\nIt provides a controlled environment to debug the linux pci subsystem\n\nReviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/Kconfig | 3 +++\n hw/arm/fsl-imx8mm.c | 30 ++++++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 10 ++++++++++\n 3 files changed, 43 insertions(+)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 74e8c431a2..59d5aba2db 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -619,11 +619,14 @@ config FSL_IMX8MP_EVK\n \n config FSL_IMX8MM\n bool\n+ imply PCI_DEVICES\n select ARM_GIC\n select FSL_IMX8MP_ANALOG\n select FSL_IMX8MP_CCM\n select IMX\n select SDHCI\n+ select PCI_EXPRESS_DESIGNWARE\n+ select PCI_EXPRESS_FSL_IMX8M_PHY\n \n config FSL_IMX8MM_EVK\n bool\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 2a4d4d5e6d..633b121630 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -184,6 +184,10 @@ static void fsl_imx8mm_init(Object *obj)\n g_autofree char *name = g_strdup_printf(\"usdhc%d\", i + 1);\n object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n }\n+\n+ object_initialize_child(obj, \"pcie\", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);\n+ object_initialize_child(obj, \"pcie_phy\", &s->pcie_phy,\n+ TYPE_FSL_IMX8M_PCIE_PHY);\n }\n \n static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n@@ -388,6 +392,30 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,\n fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);\n \n+ /* PCIe */\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_PCIE1].addr);\n+\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTA_IRQ));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTB_IRQ));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTC_IRQ));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTD_IRQ));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_MSI_IRQ));\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_PCIE_PHY1].addr);\n+\n /* Unimplemented devices */\n for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {\n switch (i) {\n@@ -395,6 +423,8 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_CCM:\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n+ case FSL_IMX8MM_PCIE1:\n+ case FSL_IMX8MM_PCIE_PHY1:\n case FSL_IMX8MM_RAM:\n case FSL_IMX8MM_OCRAM:\n case FSL_IMX8MM_SNVS_HP:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 93a30a2f55..3181c02574 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -16,6 +16,8 @@\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n+#include \"hw/pci-host/designware.h\"\n+#include \"hw/pci-host/fsl_imx8m_phy.h\"\n #include \"hw/sd/sdhci.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n@@ -44,6 +46,8 @@ struct FslImx8mmState {\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n+ DesignwarePCIEHost pcie;\n+ FslImx8mPciePhyState pcie_phy;\n };\n \n enum FslImx8mmMemoryRegions {\n@@ -166,6 +170,12 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_UART2_IRQ = 27,\n FSL_IMX8MM_UART3_IRQ = 28,\n FSL_IMX8MM_UART4_IRQ = 29,\n+\n+ FSL_IMX8MM_PCI_INTA_IRQ = 122,\n+ FSL_IMX8MM_PCI_INTB_IRQ = 123,\n+ FSL_IMX8MM_PCI_INTC_IRQ = 124,\n+ FSL_IMX8MM_PCI_INTD_IRQ = 125,\n+ FSL_IMX8MM_PCI_MSI_IRQ = 127,\n };\n \n #endif /* FSL_IMX8MM_H */\n", "prefixes": [ "PULL", "08/63" ] }