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GET /api/1.1/patches/2228817/?format=api
{ "id": 2228817, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228817/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-5-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-5-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:38", "name": "[PULL,04/63] hw/arm/fsl-imx8mm: Add Analog device IP to iMX8MM SOC", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "84447c488b6a2219895ccbedd93e435ab565c11c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-5-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228817/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228817/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=WRVZjrrS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43Kv5b05z1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:49:23 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLOG-0008Mm-BN; Mon, 27 Apr 2026 08:48:44 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNL-0007lF-8C\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400", "from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNI-0005RA-KM\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:46 -0400", "by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-4896c22fcbaso74975685e9.0\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:44 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.47.42\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 27 Apr 2026 05:47:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777294063; x=1777898863; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=ghI8DYvTSL+/rSM2e8e78x9QvBfh+Z450FrfGt1c51A=;\n b=WRVZjrrSXHuMQuAuA8vi58MReJUCZbOA5MUnnD/9CBbd6Pi+QTKsbVZaGaxqiOWLi0\n HdSMKAXHjt1DYElZAFmpQdVv/RHQMBfqBZy8+rKuJ47XFGrDsoPdmkuCRoDQBiDzW3+0\n p4c+/eCJtpTPqIe5DiuH3jOkLtpTNBVoZRnKnvG2f1ooYTItW/kRpoGdum8i0JcGPcYA\n 4F/Mr1RtfeKgQ2TQhfxGAENP4hvFre0sdopFsS1wMeDzwHvpQKrWUwFku/QJhkDpB3KZ\n 6D5ct5bC4WOND4sSWpB21WzjhPxkf9GHm/IqurkrhX+n1EuroPlBik3aQov76dIIsI6w\n 3eCw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777294063; x=1777898863;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=ghI8DYvTSL+/rSM2e8e78x9QvBfh+Z450FrfGt1c51A=;\n b=Lc/eSftTBT9KTRNGIkE7tEdgsPqRAcxrQ4bgdkQpmCVavdB3GhDqbyMKJ/qbQRZoed\n G1DetAGRduDzI9dsGHT0U2rqN9HxpStJHHDzkYnrJJY6fScdfjKexiuxHZpWItV9yFPM\n Wcw4qkq1nqhOQsbaU/LuP1jvnplPoA266pq0HzWvy25bEHJStAgHUuIZFAxKR5Y+cTNp\n BGQ2ZfyT9fKXX44/ONAwA0r/e/XB/rXfVI85lH3sC1wVOAReq1Dz7ZBHBJWpS5jvQ3Oj\n nP/C72KsiFi4uF5fQ6L+99IwpGLJuW5Fm4A9CybU6m2VCpfowojL0EBBSY4LJa9T5uU7\n gleQ==", "X-Gm-Message-State": "AOJu0YzlpIrjetTaQOOMqisCA1+h87M1uA6j15H+FEVRaoLrXgSZ03/1\n PZfvJEycwYs3wWeckaIvc3Z6fgQoI1/y0VUG//NyvNXDQzWAXrdSq3vRjy3cBN4rd+UER/wbFt6\n KOxi8", "X-Gm-Gg": "AeBDies+FWuH8jRN8MVJ/ILki03Ft56V675N0cgI/HvL4BU3SdyhYK31Gi9NKqP0jig\n 82jYQNMXEV/Rzmctzpwo5J3JKQspn47eKpcgI32FT+QhWotRATWSfbIGxiGLeY6jMKtsTBnE8ZO\n 8/wsIffDOhk0ONxcyAw7f/sRMP3LAbsg8xO8GtcJDkt/ir8MC1MnPb3pokHYcpwctu3OSMMhxmq\n VWuhA5t3QVwWaEHe0vpM2JE1PP/Me896aLzs3ys5jUdkb/SyPS5lfjw17wDCpGIFWROmekIPUrS\n n7FJQjVjSQ8d9QSzdf4n1yYR1ioziZB2Z/G3N+fFSVoUIybw3sgpztfjG957+6HvpUkMLBdACj/\n 4ZXK5+geG7LFd9p3MSXTi4c1MLypgTm4hoP+Sa3eqN+z+VrByKuo0F4l4Y+6ZgVrQ7P7fJ1YfuU\n 0ZwThRBn0GOmbPvYExQuY9qZFFmHN/bq3fVVC5kw3XecmtlcEASbfuU/lWAYWsJF3RklkoQ6xfa\n T/0sgx0ipJ7Wu32wRqperq0uuJnQ4YhgnwWoJ6HOZtDhGb4JHew", "X-Received": "by 2002:a05:600c:4e4c:b0:48a:58ae:9938 with SMTP id\n 5b1f17b1804b1-48a58ae9f69mr414383445e9.19.1777294062868;\n Mon, 27 Apr 2026 05:47:42 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 04/63] hw/arm/fsl-imx8mm: Add Analog device IP to iMX8MM SOC", "Date": "Mon, 27 Apr 2026 13:46:38 +0100", "Message-ID": "<20260427124738.966578-5-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427124738.966578-1-peter.maydell@linaro.org>", "References": "<20260427124738.966578-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nAdd the Analog IP to i.MX8MM SoC. iMX8MM and i.MX8MP uses\nthe same Analog IP so the analog ip source will be shared.\n\nThe ARM PLL divider control register (arm-pll-fdiv-ctl0) has\na different reset value on i.MX8MM (0x000fa030) compared to\ni.MX8MP (0x000fa031). So iMX8MM will be overriding this property\nwith its own reset-value.\n\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 12 ++++++++++++\n include/hw/arm/fsl-imx8mm.h | 2 ++\n 3 files changed, 15 insertions(+)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 86f4d9bc4d..b3db2d6848 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -620,6 +620,7 @@ config FSL_IMX8MP_EVK\n config FSL_IMX8MM\n bool\n select ARM_GIC\n+ select FSL_IMX8MP_ANALOG\n select IMX\n \n config FSL_IMX8MM_EVK\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 23a82613d7..8218448074 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -169,6 +169,8 @@ static void fsl_imx8mm_init(Object *obj)\n \n object_initialize_child(obj, \"gic\", &s->gic, gicv3_class_name());\n \n+ object_initialize_child(obj, \"analog\", &s->analog, TYPE_IMX8MP_ANALOG);\n+\n for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n g_autofree char *name = g_strdup_printf(\"uart%d\", i + 1);\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n@@ -303,6 +305,15 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n }\n }\n \n+ /* Analog */\n+ object_property_set_uint(OBJECT(&s->analog), \"arm-pll-fdiv-ctl0-reset\",\n+ 0x000fa030, &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_ANA_PLL].addr);\n+\n /* UARTs */\n for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n static const struct {\n@@ -338,6 +349,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n /* Unimplemented devices */\n for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {\n switch (i) {\n+ case FSL_IMX8MM_ANA_PLL:\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_RAM:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 2811e809b9..0a020c32a1 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -13,6 +13,7 @@\n #include \"cpu.h\"\n #include \"hw/char/imx_serial.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n+#include \"hw/misc/imx8mp_analog.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -33,6 +34,7 @@ struct FslImx8mmState {\n \n ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n GICv3State gic;\n+ IMX8MPAnalogState analog;\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n };\n", "prefixes": [ "PULL", "04/63" ] }