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GET /api/1.1/patches/2228814/?format=api
{ "id": 2228814, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228814/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-3-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427124738.966578-3-peter.maydell@linaro.org>", "date": "2026-04-27T12:46:36", "name": "[PULL,02/63] hw/arm: Add the i.MX 8MM EVK(Evaluation Kit) board", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "dd870edecac348e5e2f00462bf363b271b4cabfb", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427124738.966578-3-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501642, "url": "http://patchwork.ozlabs.org/api/1.1/series/501642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501642", "date": "2026-04-27T12:46:34", "name": "[PULL,01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228814/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228814/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=q7klzWfz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g43KC3Bf5z1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 22:48:47 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHLO8-00089i-P5; Mon, 27 Apr 2026 08:48:37 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNL-0007lG-9D\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400", "from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wHLNG-0005Pc-W7\n for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:46 -0400", "by mail-wm1-x32e.google.com with SMTP id\n 5b1f17b1804b1-488a88aeec9so127015785e9.2\n for <qemu-devel@nongnu.org>; Mon, 27 Apr 2026 05:47:42 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n\nImplemented CPUs, RAM, UARTs and Interrupt Controller\nOther peripherals are represented as TYPE_UNIMPLEMENTED_DEVICE\nComplete memory map of the SoC is provided.\n\nSet default RAM size to 2GB and default CPU count to 4 to match\nthe real i.MX8MM EVK hardware configuration.\n\nDocumentation is shared with imx8mp-evk to avoid duplication.\n\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n[PMM: fixed over-long lines in doc]\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Bernhard Beschow <shentey@gmail.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n MAINTAINERS | 11 +-\n docs/system/arm/{imx8mp-evk.rst => imx8m.rst} | 49 ++-\n docs/system/target-arm.rst | 2 +-\n hw/arm/Kconfig | 12 +\n hw/arm/fsl-imx8mm.c | 377 ++++++++++++++++++\n hw/arm/imx8mm-evk.c | 112 ++++++\n hw/arm/meson.build | 2 +\n include/hw/arm/fsl-imx8mm.h | 158 ++++++++\n 8 files changed, 709 insertions(+), 14 deletions(-)\n rename docs/system/arm/{imx8mp-evk.rst => imx8m.rst} (58%)\n create mode 100644 hw/arm/fsl-imx8mm.c\n create mode 100644 hw/arm/imx8mm-evk.c\n create mode 100644 include/hw/arm/fsl-imx8mm.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 35529266a2..8167d42876 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -913,6 +913,15 @@ F: hw/pci-host/designware.c\n F: include/hw/pci-host/designware.h\n F: docs/system/arm/mcimx7d-sabre.rst\n \n+MCIMX8MM-EVK / iMX8MM\n+M: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n+L: qemu-arm@nongnu.org\n+S: Maintained\n+F: hw/arm/fsl-imx8mm.c\n+F: hw/arm/imx8mm-evk.c\n+F: include/hw/arm/fsl-imx8mm.h\n+F: docs/system/arm/imx8m.rst\n+\n MCIMX8MP-EVK / i.MX8MP\n M: Bernhard Beschow <shentey@gmail.com>\n L: qemu-arm@nongnu.org\n@@ -925,7 +934,7 @@ F: hw/rtc/rs5c372.c\n F: include/hw/arm/fsl-imx8mp.h\n F: include/hw/misc/imx8mp_*.h\n F: include/hw/pci-host/fsl_imx8m_phy.h\n-F: docs/system/arm/imx8mp-evk.rst\n+F: docs/system/arm/imx8m.rst\n F: tests/functional/aarch64/test_imx8mp_evk.py\n F: tests/qtest/rs5c372-test.c\n \ndiff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8m.rst\nsimilarity index 58%\nrename from docs/system/arm/imx8mp-evk.rst\nrename to docs/system/arm/imx8m.rst\nindex e60a422824..afbc33b2f4 100644\n--- a/docs/system/arm/imx8mp-evk.rst\n+++ b/docs/system/arm/imx8m.rst\n@@ -1,13 +1,15 @@\n-NXP i.MX 8M Plus Evaluation Kit (``imx8mp-evk``)\n-================================================\n+NXP i.MX 8M Plus and i.MX 8M Mini Evaluation Kits (``imx8mp-evk``, ``imx8mm-evk``)\n+==================================================================================\n \n-The ``imx8mp-evk`` machine models the i.MX 8M Plus Evaluation Kit, based on an\n-i.MX 8M Plus SoC.\n+The ``imx8mp-evk`` and ``imx8mm-evk`` machine models the i.MX 8M Plus\n+and i.MX 8M Mini Evaluation Kits, based on i.MX 8M Plus and i.MX8M\n+Mini SoCs.\n \n Supported devices\n -----------------\n \n-The ``imx8mp-evk`` machine implements the following devices:\n+The ``imx8mp-evk`` and ``imx8mm-evk`` machines implement the\n+following devices:\n \n * Up to 4 Cortex-A53 cores\n * Generic Interrupt Controller (GICv3)\n@@ -27,8 +29,8 @@ The ``imx8mp-evk`` machine implements the following devices:\n Boot options\n ------------\n \n-The ``imx8mp-evk`` machine can start a Linux kernel directly using the standard\n-``-kernel`` functionality.\n+The ``imx8mp-evk`` and ``imx8mm-evk`` machines can start a Linux\n+kernel directly using the standard ``-kernel`` functionality.\n \n Direct Linux Kernel Boot\n ''''''''''''''''''''''''\n@@ -38,11 +40,20 @@ is to generate an image with Buildroot. Version 2024.11.1 is tested at the time\n of writing and involves two steps. First run the following commands in the\n toplevel directory of the Buildroot source tree:\n \n+For i.MX 8M Plus EVK:\n+\n .. code-block:: bash\n \n $ make freescale_imx8mpevk_defconfig\n $ make\n \n+For i.MX 8M Mini EVK:\n+\n+.. code-block:: bash\n+\n+ $ make freescale_imx8mmevk_defconfig\n+ $ make\n+\n Once finished successfully there is an ``output/image`` subfolder. Navigate into\n it and resize the SD card image to a power of two:\n \n@@ -52,6 +63,8 @@ it and resize the SD card image to a power of two:\n \n Now that everything is prepared the machine can be started as follows:\n \n+For i.MX 8M Plus EVK:\n+\n .. code-block:: bash\n \n $ qemu-system-aarch64 -M imx8mp-evk \\\n@@ -61,6 +74,16 @@ Now that everything is prepared the machine can be started as follows:\n -append \"root=/dev/mmcblk2p2\" \\\n -drive file=sdcard.img,if=sd,bus=2,format=raw,id=mmcblk2\n \n+For i.MX 8M Mini EVK:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-aarch64 -M imx8mm-evk -smp 4 -m 2G \\\n+ -display none -serial null -serial stdio \\\n+ -kernel Image \\\n+ -dtb imx8mm-evk.dtb \\\n+ -append \"root=/dev/mmcblk2p2\" \\\n+ -drive file=sdcard.img,if=sd,bus=2,format=raw,id=mmcblk2\n \n KVM Acceleration\n ----------------\n@@ -69,11 +92,13 @@ To enable hardware-assisted acceleration via KVM, append\n ``-accel kvm`` to the command line. While this speeds up performance\n significantly, be aware of the following limitations:\n \n-* The ``imx8mp-evk`` machine is not included under the \"virtualization use case\"\n- of :doc:`QEMU's security policy </system/security>`. This means that you\n- should not trust that it can contain malicious guests, whether it is run\n- using TCG or KVM. If you don't trust your guests and you're relying on QEMU to\n- be the security boundary, you want to choose another machine such as ``virt``.\n+* The ``imx8mp-evk`` and ``imx8mm-evk`` machines are not included\n+ under the \"virtualization use case\" of :doc:`QEMU's security\n+ policy </system/security>`. This means that you should not trust that\n+ it can contain malicious guests, whether it is run using TCG or KVM.\n+ If you don't trust your guests and you're relying on QEMU to be the\n+ security boundary, you want to choose another machine such as\n+ ``virt``.\n * Rather than Cortex-A53 CPUs, the same CPU type as the host's will be used.\n This is a limitation of KVM and may not work with guests with a tight\n dependency on Cortex-A53.\ndiff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst\nindex 89f7b77313..c57102a414 100644\n--- a/docs/system/target-arm.rst\n+++ b/docs/system/target-arm.rst\n@@ -95,7 +95,7 @@ Board-specific documentation\n arm/imx25-pdk\n arm/mcimx6ul-evk\n arm/mcimx7d-sabre\n- arm/imx8mp-evk\n+ arm/imx8m\n arm/orangepi\n arm/raspi\n arm/collie\ndiff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 41d5e968c8..86f4d9bc4d 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -617,6 +617,18 @@ config FSL_IMX8MP_EVK\n depends on TCG\n select FSL_IMX8MP\n \n+config FSL_IMX8MM\n+ bool\n+ select ARM_GIC\n+ select IMX\n+\n+config FSL_IMX8MM_EVK\n+ bool\n+ default y\n+ depends on AARCH64\n+ depends on TCG\n+ select FSL_IMX8MM\n+\n config ARM_SMMUV3_ACCEL\n bool\n depends on ARM_SMMUV3\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nnew file mode 100644\nindex 0000000000..23a82613d7\n--- /dev/null\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -0,0 +1,377 @@\n+/*\n+ * i.MX 8MM SoC Implementation\n+ *\n+ * Based on hw/arm/fsl-imx6.c\n+ *\n+ * Copyright (c) 2025, NXP Semiconductors\n+ * Author: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * iMX8MM Reference Manual - https://www.nxp.com/products/i.MX8MMINI -> Documentation\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"system/address-spaces.h\"\n+#include \"hw/arm/bsa.h\"\n+#include \"hw/arm/fsl-imx8mm.h\"\n+#include \"hw/misc/unimp.h\"\n+#include \"hw/core/boards.h\"\n+#include \"system/kvm.h\"\n+#include \"system/system.h\"\n+#include \"target/arm/cpu.h\"\n+#include \"target/arm/cpu-qom.h\"\n+#include \"target/arm/kvm_arm.h\"\n+#include \"qapi/error.h\"\n+#include \"qobject/qlist.h\"\n+\n+static const struct {\n+ hwaddr addr;\n+ size_t size;\n+ const char *name;\n+} fsl_imx8mm_memmap[] = {\n+ [FSL_IMX8MM_RAM] = { FSL_IMX8MM_RAM_START, FSL_IMX8MM_RAM_SIZE_MAX, \"ram\" },\n+ [FSL_IMX8MM_DDR_PHY_BROADCAST] = { 0x3dc00000, 4 * MiB, \"ddr_phy_broadcast\" },\n+ [FSL_IMX8MM_DDR_PERF_MON] = { 0x3d800000, 4 * MiB, \"ddr_perf_mon\" },\n+ [FSL_IMX8MM_DDR_CTL] = { 0x3d400000, 4 * MiB, \"ddr_ctl\" },\n+ [FSL_IMX8MM_DDR_PHY] = { 0x3c000000, 16 * MiB, \"ddr_phy\" },\n+ [FSL_IMX8MM_GIC_DIST] = { 0x38800000, 512 * KiB, \"gic_dist\" },\n+ [FSL_IMX8MM_GIC_REDIST] = { 0x38880000, 512 * KiB, \"gic_redist\" },\n+ [FSL_IMX8MM_VPU] = { 0x38340000, 2 * MiB, \"vpu\" },\n+ [FSL_IMX8MM_VPU_BLK_CTRL] = { 0x38330000, 2 * MiB, \"vpu_blk_ctrl\" },\n+ [FSL_IMX8MM_VPU_G2_DECODER] = { 0x38310000, 1 * MiB, \"vpu_g2_decoder\" },\n+ [FSL_IMX8MM_VPU_G1_DECODER] = { 0x38300000, 1 * MiB, \"vpu_g1_decoder\" },\n+ [FSL_IMX8MM_USB2_OTG] = { 0x32e50200, 0x200, \"usb2_otg\" },\n+ [FSL_IMX8MM_USB2] = { 0x32e50000, 0x200, \"usb2\" },\n+ [FSL_IMX8MM_USB1_OTG] = { 0x32e40200, 0x200, \"usb1_otg\" },\n+ [FSL_IMX8MM_USB1] = { 0x32e40000, 0x200, \"usb1\" },\n+ [FSL_IMX8MM_GPU2D] = { 0x38000000, 64 * KiB, \"gpu2d\" },\n+ [FSL_IMX8MM_QSPI1_RX_BUFFER] = { 0x34000000, 32 * MiB, \"qspi1_rx_buffer\" },\n+ [FSL_IMX8MM_PCIE1] = { 0x33800000, 4 * MiB, \"pcie1\" },\n+ [FSL_IMX8MM_QSPI1_TX_BUFFER] = { 0x33008000, 32 * KiB, \"qspi1_tx_buffer\" },\n+ [FSL_IMX8MM_APBH_DMA] = { 0x33000000, 32 * KiB, \"apbh_dma\" },\n+\n+ /* AIPS-4 Begin */\n+ [FSL_IMX8MM_TZASC] = { 0x32f80000, 64 * KiB, \"tzasc\" },\n+ [FSL_IMX8MM_PCIE_PHY1] = { 0x32f00000, 64 * KiB, \"pcie_phy1\" },\n+ [FSL_IMX8MM_MEDIA_BLK_CTL] = { 0x32e28000, 256, \"media_blk_ctl\" },\n+ [FSL_IMX8MM_LCDIF] = { 0x32e00000, 64 * KiB, \"lcdif\" },\n+ [FSL_IMX8MM_MIPI_DSI] = { 0x32e10000, 64 * KiB, \"mipi_dsi\" },\n+ [FSL_IMX8MM_MIPI_CSI] = { 0x32e30000, 64 * KiB, \"mipi_csi\" },\n+ [FSL_IMX8MM_AIPS4_CONFIGURATION] = { 0x32df0000, 64 * KiB, \"aips4_configuration\" },\n+ /* AIPS-4 End */\n+\n+ [FSL_IMX8MM_INTERCONNECT] = { 0x32700000, 1 * MiB, \"interconnect\" },\n+\n+ /* AIPS-3 Begin */\n+ [FSL_IMX8MM_ENET1] = { 0x30be0000, 64 * KiB, \"enet1\" },\n+ [FSL_IMX8MM_SDMA1] = { 0x30bd0000, 64 * KiB, \"sdma1\" },\n+ [FSL_IMX8MM_QSPI] = { 0x30bb0000, 64 * KiB, \"qspi\" },\n+ [FSL_IMX8MM_USDHC3] = { 0x30b60000, 64 * KiB, \"usdhc3\" },\n+ [FSL_IMX8MM_USDHC2] = { 0x30b50000, 64 * KiB, \"usdhc2\" },\n+ [FSL_IMX8MM_USDHC1] = { 0x30b40000, 64 * KiB, \"usdhc1\" },\n+ [FSL_IMX8MM_SEMAPHORE_HS] = { 0x30ac0000, 64 * KiB, \"semaphore_hs\" },\n+ [FSL_IMX8MM_MU_B] = { 0x30ab0000, 64 * KiB, \"mu_b\" },\n+ [FSL_IMX8MM_MU_A] = { 0x30aa0000, 64 * KiB, \"mu_a\" },\n+ [FSL_IMX8MM_UART4] = { 0x30a60000, 64 * KiB, \"uart4\" },\n+ [FSL_IMX8MM_I2C4] = { 0x30a50000, 64 * KiB, \"i2c4\" },\n+ [FSL_IMX8MM_I2C3] = { 0x30a40000, 64 * KiB, \"i2c3\" },\n+ [FSL_IMX8MM_I2C2] = { 0x30a30000, 64 * KiB, \"i2c2\" },\n+ [FSL_IMX8MM_I2C1] = { 0x30a20000, 64 * KiB, \"i2c1\" },\n+ [FSL_IMX8MM_AIPS3_CONFIGURATION] = { 0x309f0000, 64 * KiB, \"aips3_configuration\" },\n+ [FSL_IMX8MM_CAAM] = { 0x30900000, 256 * KiB, \"caam\" },\n+ [FSL_IMX8MM_SPBA1] = { 0x308f0000, 64 * KiB, \"spba1\" },\n+ [FSL_IMX8MM_UART2] = { 0x30890000, 64 * KiB, \"uart2\" },\n+ [FSL_IMX8MM_UART3] = { 0x30880000, 64 * KiB, \"uart3\" },\n+ [FSL_IMX8MM_UART1] = { 0x30860000, 64 * KiB, \"uart1\" },\n+ [FSL_IMX8MM_ECSPI3] = { 0x30840000, 64 * KiB, \"ecspi3\" },\n+ [FSL_IMX8MM_ECSPI2] = { 0x30830000, 64 * KiB, \"ecspi2\" },\n+ [FSL_IMX8MM_ECSPI1] = { 0x30820000, 64 * KiB, \"ecspi1\" },\n+ /* AIPS-3 End */\n+\n+ /* AIPS-2 Begin */\n+ [FSL_IMX8MM_QOSC] = { 0x307f0000, 64 * KiB, \"qosc\" },\n+ [FSL_IMX8MM_PERFMON2] = { 0x307d0000, 64 * KiB, \"perfmon2\" },\n+ [FSL_IMX8MM_PERFMON1] = { 0x307c0000, 64 * KiB, \"perfmon1\" },\n+ [FSL_IMX8MM_GPT4] = { 0x30700000, 64 * KiB, \"gpt4\" },\n+ [FSL_IMX8MM_GPT5] = { 0x306f0000, 64 * KiB, \"gpt5\" },\n+ [FSL_IMX8MM_GPT6] = { 0x306e0000, 64 * KiB, \"gpt6\" },\n+ [FSL_IMX8MM_SYSCNT_CTRL] = { 0x306c0000, 64 * KiB, \"syscnt_ctrl\" },\n+ [FSL_IMX8MM_SYSCNT_CMP] = { 0x306b0000, 64 * KiB, \"syscnt_cmp\" },\n+ [FSL_IMX8MM_SYSCNT_RD] = { 0x306a0000, 64 * KiB, \"syscnt_rd\" },\n+ [FSL_IMX8MM_PWM4] = { 0x30690000, 64 * KiB, \"pwm4\" },\n+ [FSL_IMX8MM_PWM3] = { 0x30680000, 64 * KiB, \"pwm3\" },\n+ [FSL_IMX8MM_PWM2] = { 0x30670000, 64 * KiB, \"pwm2\" },\n+ [FSL_IMX8MM_PWM1] = { 0x30660000, 64 * KiB, \"pwm1\" },\n+ [FSL_IMX8MM_AIPS2_CONFIGURATION] = { 0x305f0000, 64 * KiB, \"aips2_configuration\" },\n+ /* AIPS-2 End */\n+\n+ /* AIPS-1 Begin */\n+ [FSL_IMX8MM_CSU] = { 0x303e0000, 64 * KiB, \"csu\" },\n+ [FSL_IMX8MM_RDC] = { 0x303d0000, 64 * KiB, \"rdc\" },\n+ [FSL_IMX8MM_SEMAPHORE2] = { 0x303c0000, 64 * KiB, \"semaphore2\" },\n+ [FSL_IMX8MM_SEMAPHORE1] = { 0x303b0000, 64 * KiB, \"semaphore1\" },\n+ [FSL_IMX8MM_GPC] = { 0x303a0000, 64 * KiB, \"gpc\" },\n+ [FSL_IMX8MM_SRC] = { 0x30390000, 64 * KiB, \"src\" },\n+ [FSL_IMX8MM_CCM] = { 0x30380000, 64 * KiB, \"ccm\" },\n+ [FSL_IMX8MM_SNVS_HP] = { 0x30370000, 64 * KiB, \"snvs_hp\" },\n+ [FSL_IMX8MM_ANA_PLL] = { 0x30360000, 64 * KiB, \"ana_pll\" },\n+ [FSL_IMX8MM_OCOTP_CTRL] = { 0x30350000, 64 * KiB, \"ocotp_ctrl\" },\n+ [FSL_IMX8MM_IOMUXC_GPR] = { 0x30340000, 64 * KiB, \"iomuxc_gpr\" },\n+ [FSL_IMX8MM_IOMUXC] = { 0x30330000, 64 * KiB, \"iomuxc\" },\n+ [FSL_IMX8MM_GPT3] = { 0x302f0000, 64 * KiB, \"gpt3\" },\n+ [FSL_IMX8MM_GPT2] = { 0x302e0000, 64 * KiB, \"gpt2\" },\n+ [FSL_IMX8MM_GPT1] = { 0x302d0000, 64 * KiB, \"gpt1\" },\n+ [FSL_IMX8MM_SDMA2] = { 0x302c0000, 64 * KiB, \"sdma2\" },\n+ [FSL_IMX8MM_SDMA3] = { 0x302b0000, 64 * KiB, \"sdma3\" },\n+ [FSL_IMX8MM_WDOG3] = { 0x302a0000, 64 * KiB, \"wdog3\" },\n+ [FSL_IMX8MM_WDOG2] = { 0x30290000, 64 * KiB, \"wdog2\" },\n+ [FSL_IMX8MM_WDOG1] = { 0x30280000, 64 * KiB, \"wdog1\" },\n+ [FSL_IMX8MM_ANA_OSC] = { 0x30270000, 64 * KiB, \"ana_osc\" },\n+ [FSL_IMX8MM_ANA_TSENSOR] = { 0x30260000, 64 * KiB, \"ana_tsensor\" },\n+ [FSL_IMX8MM_GPIO5] = { 0x30240000, 64 * KiB, \"gpio5\" },\n+ [FSL_IMX8MM_GPIO4] = { 0x30230000, 64 * KiB, \"gpio4\" },\n+ [FSL_IMX8MM_GPIO3] = { 0x30220000, 64 * KiB, \"gpio3\" },\n+ [FSL_IMX8MM_GPIO2] = { 0x30210000, 64 * KiB, \"gpio2\" },\n+ [FSL_IMX8MM_GPIO1] = { 0x30200000, 64 * KiB, \"gpio1\" },\n+ [FSL_IMX8MM_AIPS1_CONFIGURATION] = { 0x301f0000, 64 * KiB, \"aips1_configuration\" },\n+ [FSL_IMX8MM_SAI6] = { 0x30060000, 64 * KiB, \"sai6\" },\n+ [FSL_IMX8MM_SAI5] = { 0x30050000, 64 * KiB, \"sai5\" },\n+ [FSL_IMX8MM_SAI3] = { 0x30030000, 64 * KiB, \"sai3\" },\n+ [FSL_IMX8MM_SAI2] = { 0x30020000, 64 * KiB, \"sai2\" },\n+ [FSL_IMX8MM_SAI1] = { 0x30010000, 64 * KiB, \"sai1\" },\n+\n+ /* AIPS-1 End */\n+\n+ [FSL_IMX8MM_A53_DAP] = { 0x28000000, 16 * MiB, \"a53_dap\" },\n+ [FSL_IMX8MM_PCIE1_MEM] = { 0x18000000, 128 * MiB, \"pcie1_mem\" },\n+ [FSL_IMX8MM_QSPI_MEM] = { 0x08000000, 256 * MiB, \"qspi_mem\" },\n+ [FSL_IMX8MM_OCRAM] = { 0x00900000, 256 * KiB, \"ocram\" },\n+ [FSL_IMX8MM_TCM_DTCM] = { 0x00800000, 128 * KiB, \"tcm_dtcm\" },\n+ [FSL_IMX8MM_TCM_ITCM] = { 0x007e0000, 128 * KiB, \"tcm_itcm\" },\n+ [FSL_IMX8MM_OCRAM_S] = { 0x00180000, 32 * KiB, \"ocram_s\" },\n+ [FSL_IMX8MM_CAAM_MEM] = { 0x00100000, 32 * KiB, \"caam_mem\" },\n+ [FSL_IMX8MM_BOOT_ROM_PROTECTED] = { 0x0003f000, 4 * KiB, \"boot_rom_protected\" },\n+ [FSL_IMX8MM_BOOT_ROM] = { 0x00000000, 252 * KiB, \"boot_rom\" },\n+};\n+\n+static void fsl_imx8mm_init(Object *obj)\n+{\n+ MachineState *ms = MACHINE(qdev_get_machine());\n+ FslImx8mmState *s = FSL_IMX8MM(obj);\n+ const char *cpu_type = ms->cpu_type ?: ARM_CPU_TYPE_NAME(\"cortex-a53\");\n+ int i;\n+\n+ for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX8MM_NUM_CPUS); i++) {\n+ g_autofree char *name = g_strdup_printf(\"cpu%d\", i);\n+ object_initialize_child(obj, name, &s->cpu[i], cpu_type);\n+ }\n+\n+ object_initialize_child(obj, \"gic\", &s->gic, gicv3_class_name());\n+\n+ for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"uart%d\", i + 1);\n+ object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n+ }\n+\n+}\n+\n+static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n+{\n+ MachineState *ms = MACHINE(qdev_get_machine());\n+ FslImx8mmState *s = FSL_IMX8MM(dev);\n+ DeviceState *gicdev = DEVICE(&s->gic);\n+ int i;\n+\n+ if (ms->smp.cpus > FSL_IMX8MM_NUM_CPUS) {\n+ error_setg(errp, \"%s: Only %d CPUs are supported (%d requested)\",\n+ TYPE_FSL_IMX8MM, FSL_IMX8MM_NUM_CPUS, ms->smp.cpus);\n+ return;\n+ }\n+\n+ /* CPUs */\n+ for (i = 0; i < ms->smp.cpus; i++) {\n+ /* On uniprocessor, the CBAR is set to 0 */\n+ if (ms->smp.cpus > 1 &&\n+ object_property_find(OBJECT(&s->cpu[i]), \"reset-cbar\")) {\n+ object_property_set_int(OBJECT(&s->cpu[i]), \"reset-cbar\",\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GIC_DIST].addr,\n+ &error_abort);\n+ }\n+\n+ /*\n+ * CNTFID0 base frequency in Hz of system counter\n+ */\n+ object_property_set_int(OBJECT(&s->cpu[i]), \"cntfrq\", 8000000,\n+ &error_abort);\n+\n+ if (object_property_find(OBJECT(&s->cpu[i]), \"has_el2\")) {\n+ object_property_set_bool(OBJECT(&s->cpu[i]), \"has_el2\",\n+ !kvm_enabled(), &error_abort);\n+ }\n+\n+ if (object_property_find(OBJECT(&s->cpu[i]), \"has_el3\")) {\n+ object_property_set_bool(OBJECT(&s->cpu[i]), \"has_el3\",\n+ !kvm_enabled(), &error_abort);\n+ }\n+\n+ if (i) {\n+ /*\n+ * Secondary CPUs start in powered-down state (and can be\n+ * powered up via the SRC system reset controller)\n+ */\n+ object_property_set_bool(OBJECT(&s->cpu[i]), \"start-powered-off\",\n+ true, &error_abort);\n+ }\n+\n+ if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {\n+ return;\n+ }\n+ }\n+\n+ /* GIC */\n+ {\n+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&s->gic);\n+ QList *redist_region_count;\n+ bool pmu = object_property_get_bool(OBJECT(first_cpu), \"pmu\", NULL);\n+\n+ qdev_prop_set_uint32(gicdev, \"num-cpu\", ms->smp.cpus);\n+ qdev_prop_set_uint32(gicdev, \"num-irq\",\n+ FSL_IMX8MM_NUM_IRQS + GIC_INTERNAL);\n+ redist_region_count = qlist_new();\n+ qlist_append_int(redist_region_count, ms->smp.cpus);\n+ qdev_prop_set_array(gicdev, \"redist-region-count\", redist_region_count);\n+ object_property_set_link(OBJECT(&s->gic), \"sysmem\",\n+ OBJECT(get_system_memory()), &error_fatal);\n+ if (!sysbus_realize(gicsbd, errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(gicsbd, 0, fsl_imx8mm_memmap[FSL_IMX8MM_GIC_DIST].addr);\n+ sysbus_mmio_map(gicsbd, 1, fsl_imx8mm_memmap[FSL_IMX8MM_GIC_REDIST].addr);\n+\n+ /*\n+ * Wire the outputs from each CPU's generic timer and the GICv3\n+ * maintenance interrupt signal to the appropriate GIC PPI inputs, and\n+ * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.\n+ */\n+ for (i = 0; i < ms->smp.cpus; i++) {\n+ DeviceState *cpudev = DEVICE(&s->cpu[i]);\n+ int intidbase = FSL_IMX8MM_NUM_IRQS + i * GIC_INTERNAL;\n+ qemu_irq irq;\n+\n+ /*\n+ * Mapping from the output timer irq lines from the CPU to the\n+ * GIC PPI inputs.\n+ */\n+ static const int timer_irqs[] = {\n+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,\n+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,\n+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,\n+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,\n+ };\n+\n+ for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {\n+ irq = qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]);\n+ qdev_connect_gpio_out(cpudev, j, irq);\n+ }\n+\n+ irq = qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IRQ);\n+ qdev_connect_gpio_out_named(cpudev, \"gicv3-maintenance-interrupt\",\n+ 0, irq);\n+\n+ irq = qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ);\n+ qdev_connect_gpio_out_named(cpudev, \"pmu-interrupt\", 0, irq);\n+\n+ sysbus_connect_irq(gicsbd, i,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));\n+ sysbus_connect_irq(gicsbd, i + ms->smp.cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));\n+ sysbus_connect_irq(gicsbd, i + 2 * ms->smp.cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));\n+ sysbus_connect_irq(gicsbd, i + 3 * ms->smp.cpus,\n+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));\n+\n+ if (kvm_enabled()) {\n+ if (pmu) {\n+ assert(arm_feature(&s->cpu[i].env, ARM_FEATURE_PMU));\n+ if (kvm_irqchip_in_kernel()) {\n+ kvm_arm_pmu_set_irq(&s->cpu[i], VIRTUAL_PMU_IRQ);\n+ }\n+ kvm_arm_pmu_init(&s->cpu[i]);\n+ }\n+ }\n+ }\n+ }\n+\n+ /* UARTs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } serial_table[FSL_IMX8MM_NUM_UARTS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_UART1].addr, FSL_IMX8MM_UART1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_UART2].addr, FSL_IMX8MM_UART2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_UART3].addr, FSL_IMX8MM_UART3_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_UART4].addr, FSL_IMX8MM_UART4_IRQ },\n+ };\n+\n+ qdev_prop_set_chr(DEVICE(&s->uart[i]), \"chardev\", serial_hd(i));\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,\n+ qdev_get_gpio_in(gicdev, serial_table[i].irq));\n+ }\n+\n+ /* On-Chip RAM */\n+ if (!memory_region_init_ram(&s->ocram, OBJECT(dev), \"imx8mm.ocram\",\n+ fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].size,\n+ errp)) {\n+ return;\n+ }\n+ memory_region_add_subregion(get_system_memory(),\n+ fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n+ &s->ocram);\n+\n+ /* Unimplemented devices */\n+ for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {\n+ switch (i) {\n+ case FSL_IMX8MM_GIC_DIST:\n+ case FSL_IMX8MM_GIC_REDIST:\n+ case FSL_IMX8MM_RAM:\n+ case FSL_IMX8MM_OCRAM:\n+ case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n+ /* device implemented and treated above */\n+ break;\n+\n+ default:\n+ create_unimplemented_device(fsl_imx8mm_memmap[i].name,\n+ fsl_imx8mm_memmap[i].addr,\n+ fsl_imx8mm_memmap[i].size);\n+ break;\n+ }\n+ }\n+}\n+\n+static void fsl_imx8mm_class_init(ObjectClass *oc, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n+\n+ dc->realize = fsl_imx8mm_realize;\n+\n+ dc->desc = \"i.MX 8MM SoC\";\n+}\n+\n+static const TypeInfo fsl_imx8mm_types[] = {\n+ {\n+ .name = TYPE_FSL_IMX8MM,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(FslImx8mmState),\n+ .instance_init = fsl_imx8mm_init,\n+ .class_init = fsl_imx8mm_class_init,\n+ },\n+};\n+\n+DEFINE_TYPES(fsl_imx8mm_types)\ndiff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c\nnew file mode 100644\nindex 0000000000..0a8cce8866\n--- /dev/null\n+++ b/hw/arm/imx8mm-evk.c\n@@ -0,0 +1,112 @@\n+/*\n+ * NXP i.MX 8MM Evaluation Kit System Emulation\n+ *\n+ * Copyright (c) 2025, NXP Semiconductors\n+ * Author: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"system/address-spaces.h\"\n+#include \"hw/arm/boot.h\"\n+#include \"hw/arm/fsl-imx8mm.h\"\n+#include \"hw/arm/machines-qom.h\"\n+#include \"hw/core/boards.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"system/kvm.h\"\n+#include \"system/qtest.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qapi/error.h\"\n+#include <libfdt.h>\n+\n+static void imx8mm_evk_modify_dtb(const struct arm_boot_info *info, void *fdt)\n+{\n+ int i, offset;\n+\n+ /* Temporarily disable following nodes until they are implemented */\n+ const char *nodes_to_remove[] = {\n+ \"nxp,imx8mm-fspi\",\n+ \"fsl,imx8mm-mipi-csi\",\n+ \"fsl,imx8mm-mipi-dsim\"\n+ };\n+\n+ for (i = 0; i < ARRAY_SIZE(nodes_to_remove); i++) {\n+ const char *dev_str = nodes_to_remove[i];\n+\n+ offset = fdt_node_offset_by_compatible(fdt, -1, dev_str);\n+ while (offset >= 0) {\n+ fdt_nop_node(fdt, offset);\n+ offset = fdt_node_offset_by_compatible(fdt, offset, dev_str);\n+ }\n+ }\n+\n+ /* Remove cpu-idle-states property from CPU nodes */\n+ offset = fdt_node_offset_by_compatible(fdt, -1, \"arm,cortex-a53\");\n+ while (offset >= 0) {\n+ fdt_nop_property(fdt, offset, \"cpu-idle-states\");\n+ offset = fdt_node_offset_by_compatible(fdt, offset, \"arm,cortex-a53\");\n+ }\n+\n+ if (kvm_enabled()) {\n+ /* Use system counter frequency from host CPU to fix time in guest */\n+ offset = fdt_node_offset_by_compatible(fdt, -1, \"arm,armv8-timer\");\n+ while (offset >= 0) {\n+ fdt_nop_property(fdt, offset, \"clock-frequency\");\n+ offset = fdt_node_offset_by_compatible(fdt, offset, \"arm,armv8-timer\");\n+ }\n+ }\n+}\n+\n+static void imx8mm_evk_init(MachineState *machine)\n+{\n+ static struct arm_boot_info boot_info;\n+ FslImx8mmState *s;\n+\n+ if (machine->ram_size > FSL_IMX8MM_RAM_SIZE_MAX) {\n+ error_report(\"RAM size \" RAM_ADDR_FMT \" above max supported (%08\" PRIx64 \")\",\n+ machine->ram_size, FSL_IMX8MM_RAM_SIZE_MAX);\n+ exit(1);\n+ }\n+\n+ boot_info = (struct arm_boot_info) {\n+ .loader_start = FSL_IMX8MM_RAM_START,\n+ .board_id = -1,\n+ .ram_size = machine->ram_size,\n+ .psci_conduit = QEMU_PSCI_CONDUIT_SMC,\n+ .modify_dtb = imx8mm_evk_modify_dtb,\n+ };\n+\n+ s = FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine),\n+ \"soc\", &error_fatal, NULL));\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);\n+\n+ memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START,\n+ machine->ram);\n+\n+ if (!qtest_enabled()) {\n+ arm_load_kernel(&s->cpu[0], machine, &boot_info);\n+ }\n+}\n+\n+static const char *imx8mm_evk_get_default_cpu_type(const MachineState *ms)\n+{\n+ if (kvm_enabled()) {\n+ return ARM_CPU_TYPE_NAME(\"host\");\n+ }\n+\n+ return ARM_CPU_TYPE_NAME(\"cortex-a53\");\n+}\n+\n+static void imx8mm_evk_machine_init(MachineClass *mc)\n+{\n+ mc->desc = \"NXP i.MX 8MM EVK Board\";\n+ mc->init = imx8mm_evk_init;\n+ mc->max_cpus = FSL_IMX8MM_NUM_CPUS;\n+ mc->default_cpus = FSL_IMX8MM_NUM_CPUS;\n+ mc->default_ram_size = 2 * GiB;\n+ mc->default_ram_id = \"imx8mm-evk.ram\";\n+ mc->get_default_cpu_type = imx8mm_evk_get_default_cpu_type;\n+}\n+\n+DEFINE_MACHINE_AARCH64(\"imx8mm-evk\", imx8mm_evk_machine_init)\ndiff --git a/hw/arm/meson.build b/hw/arm/meson.build\nindex 3be1252c4f..84b8ec5fb5 100644\n--- a/hw/arm/meson.build\n+++ b/hw/arm/meson.build\n@@ -84,6 +84,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c'))\n arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))\n arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'))\n arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c'))\n+arm_common_ss.add(when: 'CONFIG_FSL_IMX8MM', if_true: files('fsl-imx8mm.c'))\n+arm_common_ss.add(when: 'CONFIG_FSL_IMX8MM_EVK', if_true: files('imx8mm-evk.c'))\n arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))\n arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c'))\n stub_ss.add(files('smmuv3-accel-stubs.c'))\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nnew file mode 100644\nindex 0000000000..2811e809b9\n--- /dev/null\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -0,0 +1,158 @@\n+/*\n+ * i.MX 8MM SoC Definitions\n+ *\n+ * Copyright (c) 2025, NXP Semiconductors\n+ * Author: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef FSL_IMX8MM_H\n+#define FSL_IMX8MM_H\n+\n+#include \"cpu.h\"\n+#include \"hw/char/imx_serial.h\"\n+#include \"hw/intc/arm_gicv3_common.h\"\n+#include \"qom/object.h\"\n+#include \"qemu/units.h\"\n+\n+#define TYPE_FSL_IMX8MM \"fsl-imx8mm\"\n+OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)\n+\n+#define FSL_IMX8MM_RAM_START 0x40000000\n+#define FSL_IMX8MM_RAM_SIZE_MAX (4 * GiB)\n+\n+enum FslImx8mmConfiguration {\n+ FSL_IMX8MM_NUM_CPUS = 4,\n+ FSL_IMX8MM_NUM_IRQS = 128,\n+ FSL_IMX8MM_NUM_UARTS = 4,\n+};\n+\n+struct FslImx8mmState {\n+ SysBusDevice parent_obj;\n+\n+ ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n+ GICv3State gic;\n+ IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n+ MemoryRegion ocram;\n+};\n+\n+enum FslImx8mmMemoryRegions {\n+ FSL_IMX8MM_A53_DAP,\n+ FSL_IMX8MM_AIPS1_CONFIGURATION,\n+ FSL_IMX8MM_AIPS2_CONFIGURATION,\n+ FSL_IMX8MM_AIPS3_CONFIGURATION,\n+ FSL_IMX8MM_AIPS4_CONFIGURATION,\n+ FSL_IMX8MM_ANA_OSC,\n+ FSL_IMX8MM_ANA_PLL,\n+ FSL_IMX8MM_ANA_TSENSOR,\n+ FSL_IMX8MM_APBH_DMA,\n+ FSL_IMX8MM_BOOT_ROM,\n+ FSL_IMX8MM_BOOT_ROM_PROTECTED,\n+ FSL_IMX8MM_CAAM,\n+ FSL_IMX8MM_CAAM_MEM,\n+ FSL_IMX8MM_CCM,\n+ FSL_IMX8MM_CSU,\n+ FSL_IMX8MM_DDR_CTL,\n+ FSL_IMX8MM_DDR_PERF_MON,\n+ FSL_IMX8MM_DDR_PHY,\n+ FSL_IMX8MM_DDR_PHY_BROADCAST,\n+ FSL_IMX8MM_ECSPI1,\n+ FSL_IMX8MM_ECSPI2,\n+ FSL_IMX8MM_ECSPI3,\n+ FSL_IMX8MM_ENET1,\n+ FSL_IMX8MM_GIC_DIST,\n+ FSL_IMX8MM_GIC_REDIST,\n+ FSL_IMX8MM_GPC,\n+ FSL_IMX8MM_GPIO1,\n+ FSL_IMX8MM_GPIO2,\n+ FSL_IMX8MM_GPIO3,\n+ FSL_IMX8MM_GPIO4,\n+ FSL_IMX8MM_GPIO5,\n+ FSL_IMX8MM_GPT1,\n+ FSL_IMX8MM_GPT2,\n+ FSL_IMX8MM_GPT3,\n+ FSL_IMX8MM_GPT4,\n+ FSL_IMX8MM_GPT5,\n+ FSL_IMX8MM_GPT6,\n+ FSL_IMX8MM_GPU2D,\n+ FSL_IMX8MM_I2C1,\n+ FSL_IMX8MM_I2C2,\n+ FSL_IMX8MM_I2C3,\n+ FSL_IMX8MM_I2C4,\n+ FSL_IMX8MM_INTERCONNECT,\n+ FSL_IMX8MM_IOMUXC,\n+ FSL_IMX8MM_IOMUXC_GPR,\n+ FSL_IMX8MM_MEDIA_BLK_CTL,\n+ FSL_IMX8MM_LCDIF,\n+ FSL_IMX8MM_MIPI_CSI,\n+ FSL_IMX8MM_MIPI_DSI,\n+ FSL_IMX8MM_MU_A,\n+ FSL_IMX8MM_MU_B,\n+ FSL_IMX8MM_OCOTP_CTRL,\n+ FSL_IMX8MM_OCRAM,\n+ FSL_IMX8MM_OCRAM_S,\n+ FSL_IMX8MM_PCIE1,\n+ FSL_IMX8MM_PCIE1_MEM,\n+ FSL_IMX8MM_PCIE_PHY1,\n+ FSL_IMX8MM_PERFMON1,\n+ FSL_IMX8MM_PERFMON2,\n+ FSL_IMX8MM_PWM1,\n+ FSL_IMX8MM_PWM2,\n+ FSL_IMX8MM_PWM3,\n+ FSL_IMX8MM_PWM4,\n+ FSL_IMX8MM_QOSC,\n+ FSL_IMX8MM_QSPI,\n+ FSL_IMX8MM_QSPI1_RX_BUFFER,\n+ FSL_IMX8MM_QSPI1_TX_BUFFER,\n+ FSL_IMX8MM_QSPI_MEM,\n+ FSL_IMX8MM_RAM,\n+ FSL_IMX8MM_RDC,\n+ FSL_IMX8MM_SAI1,\n+ FSL_IMX8MM_SAI2,\n+ FSL_IMX8MM_SAI3,\n+ FSL_IMX8MM_SAI5,\n+ FSL_IMX8MM_SAI6,\n+ FSL_IMX8MM_SDMA1,\n+ FSL_IMX8MM_SDMA2,\n+ FSL_IMX8MM_SDMA3,\n+ FSL_IMX8MM_SEMAPHORE1,\n+ FSL_IMX8MM_SEMAPHORE2,\n+ FSL_IMX8MM_SEMAPHORE_HS,\n+ FSL_IMX8MM_SNVS_HP,\n+ FSL_IMX8MM_SPBA1,\n+ FSL_IMX8MM_SRC,\n+ FSL_IMX8MM_SYSCNT_CMP,\n+ FSL_IMX8MM_SYSCNT_CTRL,\n+ FSL_IMX8MM_SYSCNT_RD,\n+ FSL_IMX8MM_TCM_DTCM,\n+ FSL_IMX8MM_TCM_ITCM,\n+ FSL_IMX8MM_TZASC,\n+ FSL_IMX8MM_UART1,\n+ FSL_IMX8MM_UART2,\n+ FSL_IMX8MM_UART3,\n+ FSL_IMX8MM_UART4,\n+ FSL_IMX8MM_USB1,\n+ FSL_IMX8MM_USB2,\n+ FSL_IMX8MM_USB1_OTG,\n+ FSL_IMX8MM_USB2_OTG,\n+ FSL_IMX8MM_USDHC1,\n+ FSL_IMX8MM_USDHC2,\n+ FSL_IMX8MM_USDHC3,\n+ FSL_IMX8MM_VPU,\n+ FSL_IMX8MM_VPU_BLK_CTRL,\n+ FSL_IMX8MM_VPU_G1_DECODER,\n+ FSL_IMX8MM_VPU_G2_DECODER,\n+ FSL_IMX8MM_WDOG1,\n+ FSL_IMX8MM_WDOG2,\n+ FSL_IMX8MM_WDOG3,\n+};\n+\n+enum FslImx8mmIrqs {\n+ FSL_IMX8MM_UART1_IRQ = 26,\n+ FSL_IMX8MM_UART2_IRQ = 27,\n+ FSL_IMX8MM_UART3_IRQ = 28,\n+ FSL_IMX8MM_UART4_IRQ = 29,\n+};\n+\n+#endif /* FSL_IMX8MM_H */\n", "prefixes": [ "PULL", "02/63" ] }