Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2228612/?format=api
{ "id": 2228612, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228612/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427070312.81679-2-clamor95@gmail.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260427070312.81679-2-clamor95@gmail.com>", "date": "2026-04-27T07:03:06", "name": "[v2,1/7] dt-bindings: memory: Document Tegra114 Memory Controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c7ae5fc8843a029c82ee3c534b8834e7f5202fcd", "submitter": { "id": 84146, "url": "http://patchwork.ozlabs.org/api/1.1/people/84146/?format=api", "name": "Svyatoslav Ryhel", "email": "clamor95@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427070312.81679-2-clamor95@gmail.com/mbox/", "series": [ { "id": 501587, "url": "http://patchwork.ozlabs.org/api/1.1/series/501587/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501587", "date": "2026-04-27T07:03:06", "name": "Tegra114: implement EMC support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501587/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228612/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228612/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-13981-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KB3aeIqu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13981-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"KB3aeIqu\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.221.49", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3vgF4n61z1yJX\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 17:03:53 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 0120F3012CBE\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 07:03:43 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id C5C3F3909B5;\n\tMon, 27 Apr 2026 07:03:42 +0000 (UTC)", "from mail-wr1-f49.google.com (mail-wr1-f49.google.com\n [209.85.221.49])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id C9BF7270552\n\tfor <linux-tegra@vger.kernel.org>; Mon, 27 Apr 2026 07:03:40 +0000 (UTC)", "by mail-wr1-f49.google.com with SMTP id\n ffacd0b85a97d-43d77f60944so7258565f8f.3\n for <linux-tegra@vger.kernel.org>;\n Mon, 27 Apr 2026 00:03:40 -0700 (PDT)", "from xeon ([188.163.112.56])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e3a341sm84245734f8f.24.2026.04.27.00.03.38\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 27 Apr 2026 00:03:38 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777273422; cv=none;\n b=IwkU8n1asyBwTLD9cZqkC4qfqTPol5e4o8k470NF/Yx/7IIABhdjjhxjtQ17oCyZKFdgZlvMWMyQ4etln9Vf3wLt0ceDfrVI2YsBKEd6IPLv9R5bAoZzfQPWAN2yNrsxRU63iXkyuZ9HNkGD5r79dj/+ROddlCV1BTrUqR1nzmc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777273422; c=relaxed/simple;\n\tbh=idAm6JZdBMdmeJKkc8DR/+djQ9ywzFWWkJPRLet5UAg=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=Ht4z/uTPkGpeKMBgZV3GcxmysTkqXVQCotXZGCzcyK1GRs5gOHpjG7P9mBzCweAVToMp54So3fUTZjXeKr6RRwAGYbZ/UVXMqprPTOVp6KzPoR2swmzNsE4HLOEO29wJIhQ1VG34YD58vVxcwUcNs+Rv8Of6Sf4G9JPKyEOpxG4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com;\n spf=pass smtp.mailfrom=gmail.com;\n dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=KB3aeIqu; arc=none smtp.client-ip=209.85.221.49", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777273419; x=1777878219;\n darn=vger.kernel.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=DpcczuyftVggiNXKRP50iSyYabcce+E3E5UaiR04aCg=;\n b=KB3aeIqu+k6wjtgWAvZZ5+fbBzMjyAc3o4UPrFONlG2+JjdtpxLE160mmF5G6WVBmO\n zPbFHTCo6peZiWtF4CfitBDPOSt04KL/llEfhmMPrucyu+3tYB+OrrgJAmYwFEWVPLtP\n SeiUjiqtkQsL5BJxhED6g2pE7RStgd1vbSZYxXXoQAE7SXOUP8H2XNJYVVQKv9LZMxyh\n ovolkxMEiF0BVxpdOp20E4Vfd8bBNk5h5OD30bXfIWIJoGueUT8W09D1CkXtgFcbur3Q\n j7yi9DMuWuibN/qQWMGjhR7hftlsHQ9fpK+IfefmXORfY5jMFJyqrN5+RZSfYkxZdLAm\n uHDw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777273419; x=1777878219;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=DpcczuyftVggiNXKRP50iSyYabcce+E3E5UaiR04aCg=;\n b=q2EJ7YWP1mUqffCOZP4QuORy+rjL7kmeFcZU+4EZFhweBWm6lk3hpQkro9yaouPcVH\n NAdWM+BpRNUaJQ/rMDqJJrnW7nekzy3wQMAs+VRPNh/+YYkD3gnzauT8xYX2Tx80Fx6q\n A8Ij7FqkrrFry5VQ4GTvlCeS4b+OE3ObPjkQQU5qKajFcGpp9cJVizScVxC9ThPa2NoX\n H67X6SMmAHgxbwBIFYukLfuaRxxBHkERiZLfvy9gcz79s0DKNcluvq+zb+c4QISOoTPH\n XQutz1WKLZQh/Iz/ipleol8YS7QUPz7d1SCTY2wlWAkKYgeNMb1ZS91/IqPFSltYUJNg\n 5Bew==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ+JRThxhrExe2CYeizThYk3qaS3yy4ZgNUMwH8JshF2ECDi0VwBlS9AjZ43Xh+4DEuPAsQ0zZvzr8iRPQ==@vger.kernel.org", "X-Gm-Message-State": "AOJu0YyGf/ngk823nyLe6EeeNwwUYiWZvD3hlj6aGR9eL7aEVgvkfpvY\n\t3tGQEV3UJsPyPZtYh6pIBRG3/c6cOUDBReWN6ZtZAklXQhq7hbXuMZXG", "X-Gm-Gg": "AeBDies7tC6bQGR88XQCbjXfvLdor1YnSNZdD6yifBeD8+A2f/R+7zbH6YQY+jJMioa\n\t103oU7UMuCbr1198ag+GGCfn2PT/PGo0N++3rWuHf9O2WjHks4DnumeetIxVcKNOInJgkv7wpwN\n\tSJ9QKu7Ngw6Z7/RkypRe2ii0npbohD9yz/jN4PtY1CE7rurLNR2hZdZGe9aE4NOtdFeIMDv83Ct\n\tMownzx4sERu7jUfyKv5VQwGj63JvBWKkILSRe+nLdCMRNLi2AJmjoTabyZHac08WHMnzcYDo4WN\n\tuQBeOHbjp4QQRCmSLOO9zOsCmly5EbEZ0gZjHxXDW+UQqjirdpDB/TsCPTaNV5ecjuoygxLvCnt\n\tmp11v8ggpFx+kV7Pj7ixGNdeGU2QxfV58J2qGhzjXTT4RntTchWv1KRKBdbYjm61Cn5hkLv/hxL\n\taSq6m5nGnJqT1jMhN2bpikNtI=", "X-Received": "by 2002:a05:6000:25c6:b0:43d:7af0:3a7c with SMTP id\n ffacd0b85a97d-43fe3e0d44emr62264642f8f.29.1777273419087;\n Mon, 27 Apr 2026 00:03:39 -0700 (PDT)", "From": "Svyatoslav Ryhel <clamor95@gmail.com>", "To": "Krzysztof Kozlowski <krzk@kernel.org>,\n\tRob Herring <robh@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tSvyatoslav Ryhel <clamor95@gmail.com>", "Cc": "linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org", "Subject": "[PATCH v2 1/7] dt-bindings: memory: Document Tegra114 Memory\n Controller", "Date": "Mon, 27 Apr 2026 10:03:06 +0300", "Message-ID": "<20260427070312.81679-2-clamor95@gmail.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20260427070312.81679-1-clamor95@gmail.com>", "References": "<20260427070312.81679-1-clamor95@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Add Tegra114 support into existing Tegra124 MC schema with the most\nnotable difference in the amount of EMEM timings.\n\nEach memory client has unique hardware ID, add these IDs.\n\nSigned-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\n---\n .../nvidia,tegra124-mc.yaml | 31 +++------\n include/dt-bindings/memory/tegra114-mc.h | 67 +++++++++++++++++++\n 2 files changed, 75 insertions(+), 23 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\nindex 7b18b4d11e0a..f8747cebb680 100644\n--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n@@ -19,7 +19,9 @@ description: |\n \n properties:\n compatible:\n- const: nvidia,tegra124-mc\n+ enum:\n+ - nvidia,tegra114-mc\n+ - nvidia,tegra124-mc\n \n reg:\n maxItems: 1\n@@ -64,29 +66,12 @@ patternProperties:\n \n nvidia,emem-configuration:\n $ref: /schemas/types.yaml#/definitions/uint32-array\n- description: |\n+ description:\n Values to be written to the EMEM register block. See section\n- \"15.6.1 MC Registers\" in the TRM.\n- items:\n- - description: MC_EMEM_ARB_CFG\n- - description: MC_EMEM_ARB_OUTSTANDING_REQ\n- - description: MC_EMEM_ARB_TIMING_RCD\n- - description: MC_EMEM_ARB_TIMING_RP\n- - description: MC_EMEM_ARB_TIMING_RC\n- - description: MC_EMEM_ARB_TIMING_RAS\n- - description: MC_EMEM_ARB_TIMING_FAW\n- - description: MC_EMEM_ARB_TIMING_RRD\n- - description: MC_EMEM_ARB_TIMING_RAP2PRE\n- - description: MC_EMEM_ARB_TIMING_WAP2PRE\n- - description: MC_EMEM_ARB_TIMING_R2R\n- - description: MC_EMEM_ARB_TIMING_W2W\n- - description: MC_EMEM_ARB_TIMING_R2W\n- - description: MC_EMEM_ARB_TIMING_W2R\n- - description: MC_EMEM_ARB_DA_TURNS\n- - description: MC_EMEM_ARB_DA_COVERS\n- - description: MC_EMEM_ARB_MISC0\n- - description: MC_EMEM_ARB_MISC1\n- - description: MC_EMEM_ARB_RING1_THROTTLE\n+ \"20.11.1 MC Registers\" in the Tegea114 TRM or\n+ \"15.6.1 MC Registers\" in the Tegra124 TRM.\n+ minItems: 18\n+ maxItems: 19\n \n required:\n - clock-frequency\ndiff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h\nindex dfe99c8a5ba5..5e0d6a1b91f2 100644\n--- a/include/dt-bindings/memory/tegra114-mc.h\n+++ b/include/dt-bindings/memory/tegra114-mc.h\n@@ -40,4 +40,71 @@\n #define TEGRA114_MC_RESET_VDE\t\t14\n #define TEGRA114_MC_RESET_VI\t\t15\n \n+#define TEGRA114_MC_PTCR\t\t0\n+#define TEGRA114_MC_DISPLAY0A\t\t1\n+#define TEGRA114_MC_DISPLAY0AB\t\t2\n+#define TEGRA114_MC_DISPLAY0B\t\t3\n+#define TEGRA114_MC_DISPLAY0BB\t\t4\n+#define TEGRA114_MC_DISPLAY0C\t\t5\n+#define TEGRA114_MC_DISPLAY0CB\t\t6\n+#define TEGRA114_MC_DISPLAY1B\t\t7\n+#define TEGRA114_MC_DISPLAY1BB\t\t8\n+#define TEGRA114_MC_EPPUP\t\t9\n+#define TEGRA114_MC_G2PR\t\t10\n+#define TEGRA114_MC_G2SR\t\t11\n+#define TEGRA114_MC_MPEUNIFBR\t\t12\n+#define TEGRA114_MC_VIRUV\t\t13\n+#define TEGRA114_MC_AFIR\t\t14\n+#define TEGRA114_MC_AVPCARM7R\t\t15\n+#define TEGRA114_MC_DISPLAYHC\t\t16\n+#define TEGRA114_MC_DISPLAYHCB\t\t17\n+#define TEGRA114_MC_FDCDRD\t\t18\n+#define TEGRA114_MC_FDCDRD2\t\t19\n+#define TEGRA114_MC_G2DR\t\t20\n+#define TEGRA114_MC_HDAR\t\t21\n+#define TEGRA114_MC_HOST1XDMAR\t\t22\n+#define TEGRA114_MC_HOST1XR\t\t23\n+#define TEGRA114_MC_IDXSRD\t\t24\n+#define TEGRA114_MC_IDXSRD2\t\t25\n+#define TEGRA114_MC_MPE_IPRED\t\t26\n+#define TEGRA114_MC_MPEAMEMRD\t\t27\n+#define TEGRA114_MC_MPECSRD\t\t28\n+#define TEGRA114_MC_PPCSAHBDMAR\t\t29\n+#define TEGRA114_MC_PPCSAHBSLVR\t\t30\n+#define TEGRA114_MC_SATAR\t\t31\n+#define TEGRA114_MC_TEXSRD\t\t32\n+#define TEGRA114_MC_TEXSRD2\t\t33\n+#define TEGRA114_MC_VDEBSEVR\t\t34\n+#define TEGRA114_MC_VDEMBER\t\t35\n+#define TEGRA114_MC_VDEMCER\t\t36\n+#define TEGRA114_MC_VDETPER\t\t37\n+#define TEGRA114_MC_MPCORELPR\t\t38\n+#define TEGRA114_MC_MPCORER\t\t39\n+#define TEGRA114_MC_EPPU\t\t40\n+#define TEGRA114_MC_EPPV\t\t41\n+#define TEGRA114_MC_EPPY\t\t42\n+#define TEGRA114_MC_MPEUNIFBW\t\t43\n+#define TEGRA114_MC_VIWSB\t\t44\n+#define TEGRA114_MC_VIWU\t\t45\n+#define TEGRA114_MC_VIWV\t\t46\n+#define TEGRA114_MC_VIWY\t\t47\n+#define TEGRA114_MC_G2DW\t\t48\n+#define TEGRA114_MC_AFIW\t\t49\n+#define TEGRA114_MC_AVPCARM7W\t\t50\n+#define TEGRA114_MC_FDCDWR\t\t51\n+#define TEGRA114_MC_FDCDWR2\t\t52\n+#define TEGRA114_MC_HDAW\t\t53\n+#define TEGRA114_MC_HOST1XW\t\t54\n+#define TEGRA114_MC_ISPW\t\t55\n+#define TEGRA114_MC_MPCORELPW\t\t56\n+#define TEGRA114_MC_MPCOREW\t\t57\n+#define TEGRA114_MC_MPECSWR\t\t58\n+#define TEGRA114_MC_PPCSAHBDMAW\t\t59\n+#define TEGRA114_MC_PPCSAHBSLVW\t\t60\n+#define TEGRA114_MC_SATAW\t\t61\n+#define TEGRA114_MC_VDEBSEVW\t\t62\n+#define TEGRA114_MC_VDEDBGW\t\t63\n+#define TEGRA114_MC_VDEMBEW\t\t64\n+#define TEGRA114_MC_VDETPMW\t\t65\n+\n #endif\n", "prefixes": [ "v2", "1/7" ] }