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GET /api/1.1/patches/2228601/?format=api
{ "id": 2228601, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228601/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-10-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427060928.2322570-10-max.chou@sifive.com>", "date": "2026-04-27T06:09:28", "name": "[v5,9/9] disas/riscv: Add support of Zvfofp8min extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1ec4917bb62ccaa3c45707871b5ea9336b57bc8c", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/1.1/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-10-max.chou@sifive.com/mbox/", "series": [ { "id": 501579, "url": "http://patchwork.ozlabs.org/api/1.1/series/501579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501579", "date": "2026-04-27T06:09:19", "name": "target/riscv: Add RISC-V Zvfofp8min extension support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228601/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228601/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=iyGDXtmG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x1031.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This patch adds support to disassemble Zvfofp8min instructions.\n\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n disas/riscv.c | 9 +++++++++\n 1 file changed, 9 insertions(+)", "diff": "diff --git a/disas/riscv.c b/disas/riscv.c\nindex d416a4d6b3..8a169deba0 100644\n--- a/disas/riscv.c\n+++ b/disas/riscv.c\n@@ -985,6 +985,9 @@ typedef enum {\n rv_op_ssamoswap_d = 953,\n rv_op_c_sspush = 954,\n rv_op_c_sspopchk = 955,\n+ rv_op_vfncvtbf16_sat_f_f_w = 956,\n+ rv_op_vfncvt_f_f_q = 957,\n+ rv_op_vfncvt_sat_f_f_q = 958,\n } rv_op;\n \n /* register names */\n@@ -2255,6 +2258,9 @@ const rv_opcode_data rvi_opcode_data[] = {\n rv_op_sspush, 0 },\n { \"c.sspopchk\", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,\n rv_op_sspopchk, 0 },\n+ { \"vfncvtbf16.sat.f.f.w\", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },\n+ { \"vfncvt.f.f.q\", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },\n+ { \"vfncvt.sat.f.f.q\", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },\n };\n \n /* CSR names */\n@@ -3631,7 +3637,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)\n case 21: op = rv_op_vfncvt_rod_f_f_w; break;\n case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;\n case 23: op = rv_op_vfncvt_rtz_x_f_w; break;\n+ case 25: op = rv_op_vfncvt_f_f_q; break;\n+ case 27: op = rv_op_vfncvt_sat_f_f_q; break;\n case 29: op = rv_op_vfncvtbf16_f_f_w; break;\n+ case 31: op = rv_op_vfncvtbf16_sat_f_f_w; break;\n }\n break;\n case 19:\n", "prefixes": [ "v5", "9/9" ] }