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GET /api/1.1/patches/2228600/?format=api
{ "id": 2228600, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228600/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-8-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427060928.2322570-8-max.chou@sifive.com>", "date": "2026-04-27T06:09:26", "name": "[v5,7/9] target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions for Zvfofp8min extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8e0e2cefad0cad6fa8ce19c520a798ccfce9aa39", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/1.1/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-8-max.chou@sifive.com/mbox/", "series": [ { "id": 501579, "url": "http://patchwork.ozlabs.org/api/1.1/series/501579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501579", "date": "2026-04-27T06:09:19", "name": "target/riscv: Add RISC-V Zvfofp8min extension support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228600/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228600/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=GQiKW7N5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The vfncvt.f.f.q and vfncvt.sat.f.f.q instructions convert a vector of\nFP32 elements to a vector of OFP8 elements. The vfncvt.sat.f.fq instruction\nconverts a vector of FP32 elements to a vector of OFP8 elements with saturation.\nThe VTYPE.altfmt field is used to select the OFP8 format.\n* altfmt = 0: FP32 to OFP8.e4m3\n* altfmt = 1: FP32 to OFP8.e5m2\n\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/insn32.decode | 2 +\n target/riscv/insn_trans/trans_rvofp8.c.inc | 63 ++++++++++++++++++++++\n target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++++++++\n 3 files changed, 104 insertions(+)", "diff": "diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\nindex 49201c0c20..f2b413c7d4 100644\n--- a/target/riscv/insn32.decode\n+++ b/target/riscv/insn32.decode\n@@ -974,6 +974,8 @@ vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm\n vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm\n \n # *** Zvfofp8min Extension ***\n+vfncvt_f_f_q 010010 . ..... 11001 001 ..... 1010111 @r2_vm\n+vfncvt_sat_f_f_q 010010 . ..... 11011 001 ..... 1010111 @r2_vm\n vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm\n \n # *** Zvbc vector crypto extension ***\ndiff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn_trans/trans_rvofp8.c.inc\nindex d28f92e050..619ee4d773 100644\n--- a/target/riscv/insn_trans/trans_rvofp8.c.inc\n+++ b/target/riscv/insn_trans/trans_rvofp8.c.inc\n@@ -12,6 +12,13 @@\n } \\\n } while (0)\n \n+static bool zvfofp8min_narrow_quad_check(DisasContext *s, arg_rmr *a)\n+{\n+ return require_rvv(s) &&\n+ vext_check_isa_ill(s) &&\n+ vext_check_sq(s, a->rd, a->rs2, a->vm) &&\n+ (s->sew == MO_8);\n+}\n \n static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a)\n {\n@@ -40,3 +47,59 @@ static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a)\n }\n return false;\n }\n+\n+static bool trans_vfncvt_f_f_q(DisasContext *ctx, arg_rmr *a)\n+{\n+ REQUIRE_FPU;\n+ REQUIRE_ZVFOFP8MIN(ctx);\n+\n+ if (zvfofp8min_narrow_quad_check(ctx, a)) {\n+ gen_helper_gvec_3_ptr *fn;\n+ uint32_t data = 0;\n+\n+ fn = ctx->altfmt ? gen_helper_vfncvt_f_f_q_ofp8e5m2 :\n+ gen_helper_vfncvt_f_f_q_ofp8e4m3;\n+\n+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);\n+\n+ data = FIELD_DP32(data, VDATA, VM, a->vm);\n+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);\n+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);\n+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);\n+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),\n+ vreg_ofs(ctx, a->rs2), tcg_env,\n+ ctx->cfg_ptr->vlenb,\n+ ctx->cfg_ptr->vlenb, data, fn);\n+ finalize_rvv_inst(ctx);\n+ return true;\n+ }\n+ return false;\n+}\n+\n+static bool trans_vfncvt_sat_f_f_q(DisasContext *ctx, arg_rmr *a)\n+{\n+ REQUIRE_FPU;\n+ REQUIRE_ZVFOFP8MIN(ctx);\n+\n+ if (zvfofp8min_narrow_quad_check(ctx, a)) {\n+ gen_helper_gvec_3_ptr *fn;\n+ uint32_t data = 0;\n+\n+ fn = ctx->altfmt ? gen_helper_vfncvt_sat_f_f_q_ofp8e5m2 :\n+ gen_helper_vfncvt_sat_f_f_q_ofp8e4m3;\n+\n+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);\n+\n+ data = FIELD_DP32(data, VDATA, VM, a->vm);\n+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);\n+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);\n+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);\n+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),\n+ vreg_ofs(ctx, a->rs2), tcg_env,\n+ ctx->cfg_ptr->vlenb,\n+ ctx->cfg_ptr->vlenb, data, fn);\n+ finalize_rvv_inst(ctx);\n+ return true;\n+ }\n+ return false;\n+}\ndiff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 5b72926b3c..2108a0fd4c 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -621,6 +621,45 @@ static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)\n require_align(vs1, s->lmul);\n }\n \n+/*\n+ * Common check function for vector narrowing instructions\n+ * of single-width result (SEW) and quad-width source (4*SEW).\n+ *\n+ * Rules to be checked here:\n+ * 1. The largest vector register group used by an instruction\n+ * can not be greater than 8 vector registers\n+ * (Section 31.5.2)\n+ * 2. Quad-width SEW cannot greater than ELEN.\n+ * (Section 31.2)\n+ * 3. Source vector register number is multiples of 4 * LMUL.\n+ * (Section 31.3.4.2)\n+ * 4. Destination vector register number is multiples of LMUL.\n+ * (Section 31.3.4.2)\n+ * 5. Destination vector register group for a masked vector\n+ * instruction cannot overlap the source mask register (v0).\n+ * (Section 31.5.3)\n+ * risc-v unprivileged spec\n+ */\n+static bool vext_quad_narrow_check_common(DisasContext *s, int vd, int vs2,\n+ int vm)\n+{\n+ return (s->lmul <= 1) &&\n+ (s->sew < MO_32) &&\n+ ((s->sew + 2) <= (s->cfg_ptr->elen >> 4)) &&\n+ require_align(vs2, s->lmul + 2) &&\n+ require_align(vd, s->lmul) &&\n+ require_vm(vm, vd);\n+}\n+\n+static bool vext_check_sq(DisasContext *s, int vd, int vs, int vm)\n+{\n+ bool ret = vext_quad_narrow_check_common(s, vd, vs, vm);\n+ if (vd != vs) {\n+ ret &= require_noover(vd, s->lmul, vs, s->lmul + 2);\n+ }\n+ return ret;\n+}\n+\n /*\n * Check function for vector reduction instructions.\n *\n", "prefixes": [ "v5", "7/9" ] }