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GET /api/1.1/patches/2228598/?format=api
{ "id": 2228598, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228598/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-7-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427060928.2322570-7-max.chou@sifive.com>", "date": "2026-04-27T06:09:25", "name": "[v5,6/9] target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "79a331ef8e276370d5ee4b44ec48efeffdc5c7bb", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/1.1/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-7-max.chou@sifive.com/mbox/", "series": [ { "id": 501579, "url": "http://patchwork.ozlabs.org/api/1.1/series/501579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501579", "date": "2026-04-27T06:09:19", "name": "target/riscv: Add RISC-V Zvfofp8min extension support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228598/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228598/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=JaldVvF9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The vfncvtbf16.sat.f.f.w instruction converts a vector of 16-bit\nfloating-point numbers to a vector of 8-bit floating-point numbers with\nsaturation.\nThe VTYPE.altfmt field is used to select the format of the 8-bit floating-point\nnumbers.\n* altfmt = 0: BF16 to OFP8.e4m3\n* altfmt = 1: BF16 to OFP8.e5m2\n\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/insn32.decode | 3 ++\n target/riscv/insn_trans/trans_rvofp8.c.inc | 42 ++++++++++++++++++++++\n target/riscv/translate.c | 1 +\n 3 files changed, 46 insertions(+)\n create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc", "diff": "diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\nindex 6e35c4b1e6..49201c0c20 100644\n--- a/target/riscv/insn32.decode\n+++ b/target/riscv/insn32.decode\n@@ -973,6 +973,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm\n vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm\n vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm\n \n+# *** Zvfofp8min Extension ***\n+vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm\n+\n # *** Zvbc vector crypto extension ***\n vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm\n vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm\ndiff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn_trans/trans_rvofp8.c.inc\nnew file mode 100644\nindex 0000000000..d28f92e050\n--- /dev/null\n+++ b/target/riscv/insn_trans/trans_rvofp8.c.inc\n@@ -0,0 +1,42 @@\n+/*\n+ * RISC-V translation routines for the OFP8 Standard Extensions.\n+ *\n+ * Copyright (C) 2025 SiFive, Inc.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#define REQUIRE_ZVFOFP8MIN(ctx) do { \\\n+ if (!ctx->cfg_ptr->ext_zvfofp8min) { \\\n+ return false; \\\n+ } \\\n+} while (0)\n+\n+\n+static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a)\n+{\n+ REQUIRE_FPU;\n+ REQUIRE_ZVFOFP8MIN(ctx);\n+\n+ if (opfv_narrow_check(ctx, a) && ctx->sew == MO_8) {\n+ gen_helper_gvec_3_ptr *fn;\n+ uint32_t data = 0;\n+\n+ fn = ctx->altfmt ? gen_helper_vfncvtbf16_sat_f_f_w_ofp8e5m2 :\n+ gen_helper_vfncvtbf16_sat_f_f_w_ofp8e4m3;\n+\n+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);\n+\n+ data = FIELD_DP32(data, VDATA, VM, a->vm);\n+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);\n+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);\n+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);\n+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),\n+ vreg_ofs(ctx, a->rs2), tcg_env,\n+ ctx->cfg_ptr->vlenb,\n+ ctx->cfg_ptr->vlenb, data, fn);\n+ finalize_rvv_inst(ctx);\n+ return true;\n+ }\n+ return false;\n+}\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 81087e0a5d..88d6efbc80 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -1220,6 +1220,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)\n #include \"insn_trans/trans_privileged.c.inc\"\n #include \"insn_trans/trans_svinval.c.inc\"\n #include \"insn_trans/trans_rvbf16.c.inc\"\n+#include \"insn_trans/trans_rvofp8.c.inc\"\n #include \"decode-xthead.c.inc\"\n #include \"decode-xmips.c.inc\"\n #include \"decode-xlrbr.c.inc\"\n", "prefixes": [ "v5", "6/9" ] }