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GET /api/1.1/patches/2228597/?format=api
{ "id": 2228597, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228597/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-4-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427060928.2322570-4-max.chou@sifive.com>", "date": "2026-04-27T06:09:22", "name": "[v5,3/9] target/riscv: Add implied rules for Zvfofp8min extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e90809b126249b419356d1484270ac6431ff7cb9", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/1.1/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-4-max.chou@sifive.com/mbox/", "series": [ { "id": 501579, "url": "http://patchwork.ozlabs.org/api/1.1/series/501579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501579", "date": "2026-04-27T06:09:19", "name": "target/riscv: Add RISC-V Zvfofp8min extension support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228597/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228597/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=T8xx0fTY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x1035.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add implied rules to enable the implied extensions of Zvfofp8min\nextension recursively.\n\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/cpu.c | 13 +++++++++++--\n 1 file changed, 11 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 855c6bd4a9..3746c79b01 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2512,6 +2512,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {\n },\n };\n \n+static RISCVCPUImpliedExtsRule ZVFOFP8MIN_IMPLIED = {\n+ .ext = CPU_CFG_OFFSET(ext_zvfofp8min),\n+ .implied_multi_exts = {\n+ CPU_CFG_OFFSET(ext_zve32f),\n+\n+ RISCV_IMPLIED_EXTS_RULE_END\n+ },\n+};\n+\n static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {\n .ext = CPU_CFG_OFFSET(ext_zvkn),\n .implied_multi_exts = {\n@@ -2649,8 +2658,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,\n &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED,\n &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,\n- &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,\n- &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,\n+ &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP8MIN_IMPLIED,\n+ &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,\n &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,\n &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED,\n NULL\n", "prefixes": [ "v5", "3/9" ] }