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GET /api/1.1/patches/2228595/?format=api
{ "id": 2228595, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228595/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-5-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427060928.2322570-5-max.chou@sifive.com>", "date": "2026-04-27T06:09:23", "name": "[v5,4/9] target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 conversion for Zvfofp8min extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "886ad158bfb6c428cf70d4cd3bd0bbc2c1bf85f4", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/1.1/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-5-max.chou@sifive.com/mbox/", "series": [ { "id": 501579, "url": "http://patchwork.ozlabs.org/api/1.1/series/501579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501579", "date": "2026-04-27T06:09:19", "name": "target/riscv: Add RISC-V Zvfofp8min extension support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228595/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228595/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n 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K934rPpIiBUZAQmJr+HW2cjXOqWhK0qa2/e5f4SBZuLYmSeLLOj/J+Ty2F9vFP636XOWDaoO7pW\n sCCWee0UakAMsQisQzcRWYQs00uVGynGKot3ZcKgNEO4fz2bo0Px+XAMSJFB5DE7U4U2GrmxneT\n 7rkklpP/uvjgcjTG2rA7lHKFy0VxQztYt0yGA==", "X-Received": "by 2002:a17:90b:3882:b0:361:3224:2f5f with SMTP id\n 98e67ed59e1d1-3614049c8a4mr46151622a91.22.1777270188700;\n Sun, 26 Apr 2026 23:09:48 -0700 (PDT)", "From": "Max Chou <max.chou@sifive.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-riscv@nongnu.org", "Cc": "Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <Alistair.Francis@wdc.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Weiwei Li <liwei1518@gmail.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Max Chou <max.chou@sifive.com>,\n Alistair Francis <alistair.francis@wdc.com>", "Subject": "[PATCH v5 4/9] target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8\n to BF16 conversion for Zvfofp8min extension", "Date": "Mon, 27 Apr 2026 14:09:23 +0800", "Message-ID": "<20260427060928.2322570-5-max.chou@sifive.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427060928.2322570-1-max.chou@sifive.com>", "References": "<20260427060928.2322570-1-max.chou@sifive.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1036;\n envelope-from=max.chou@sifive.com; helo=mail-pj1-x1036.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "According to the Zvfofp8min extension, the vfwcvtbf16.f.f.v instruction\nsupports OFP8 to BF16 conversion when SEW is 8.\nAnd the VTYPE.altfmt field is used to select the OFP8 format.\n* altfmt = 0: OFP8.e4m3 to BF16\n* altfmt = 1: OFP8.e5m2 to BF16\n\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/helper.h | 12 +++\n target/riscv/insn_trans/trans_rvbf16.c.inc | 16 +++-\n target/riscv/vector_helper.c | 99 +++++++++++++++++++++-\n 3 files changed, 122 insertions(+), 5 deletions(-)", "diff": "diff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex 54d2331966..508314e154 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -1249,6 +1249,18 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32)\n DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32)\n \n+/* OFP8 functions */\n+DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e4m3, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e5m2, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvt_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvt_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32)\n+\n /* Vector crypto functions */\n DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)\n DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)\ndiff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc\nindex 066dc364c5..86eb86f615 100644\n--- a/target/riscv/insn_trans/trans_rvbf16.c.inc\n+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc\n@@ -92,11 +92,20 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)\n static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)\n {\n REQUIRE_FPU;\n- REQUIRE_ZVFBFMIN(ctx);\n \n- if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {\n+ if (opfv_widen_check(ctx, a) &&\n+ ((ctx->sew == MO_16 && ctx->cfg_ptr->ext_zvfbfmin) ||\n+ (ctx->sew == MO_8 && ctx->cfg_ptr->ext_zvfofp8min))) {\n+ gen_helper_gvec_3_ptr *fn;\n uint32_t data = 0;\n \n+ if (ctx->sew == MO_16) {\n+ fn = gen_helper_vfwcvtbf16_f_f_v;\n+ } else {\n+ fn = ctx->altfmt ? gen_helper_vfwcvtbf16_f_f_v_ofp8e5m2 :\n+ gen_helper_vfwcvtbf16_f_f_v_ofp8e4m3;\n+ }\n+\n gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);\n \n data = FIELD_DP32(data, VDATA, VM, a->vm);\n@@ -106,8 +115,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)\n tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),\n vreg_ofs(ctx, a->rs2), tcg_env,\n ctx->cfg_ptr->vlenb,\n- ctx->cfg_ptr->vlenb, data,\n- gen_helper_vfwcvtbf16_f_f_v);\n+ ctx->cfg_ptr->vlenb, data, fn);\n finalize_rvv_inst(ctx);\n return true;\n }\ndiff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\nindex 73437c1d20..e7925f387b 100644\n--- a/target/riscv/vector_helper.c\n+++ b/target/riscv/vector_helper.c\n@@ -89,7 +89,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n \n switch (vsew) {\n case MO_8:\n- ill_altfmt &= !(cpu->cfg.ext_zvfbfa);\n+ ill_altfmt &= !(cpu->cfg.ext_zvfbfa || cpu->cfg.ext_zvfofp8min);\n break;\n case MO_16:\n ill_altfmt &= !(cpu->cfg.ext_zvfbfa);\n@@ -5025,6 +5025,103 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)\n RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16)\n GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2)\n \n+/*\n+ * OCP FP8 Narrowing Conversions (BF16/F32 -> FP8)\n+ * 1. Initialize a local float_status with RISC-V specific NaN handling\n+ * 2. Call the softfloat conversion function with saturation parameter\n+ * 3. Merge exception flags back to the original status\n+ */\n+#define GEN_OCP_FP8_NARROW(NAME, CONVERT_FN, SATURATE, IN_TYPE) \\\n+static uint8_t NAME(IN_TYPE a, float_status *s) \\\n+{ \\\n+ float_status local = *s; \\\n+ local.default_nan_pattern = 0x70; \\\n+ local.default_nan_mode = true; \\\n+ uint8_t result = CONVERT_FN(a, SATURATE, &local); \\\n+ s->float_exception_flags |= local.float_exception_flags; \\\n+ return result; \\\n+}\n+\n+/* BF16 -> E4M3/E5M2 conversions */\n+GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e4m3, bfloat16_to_float8_e4m3, false,\n+ uint16_t)\n+GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e5m2, bfloat16_to_float8_e5m2, false,\n+ uint16_t)\n+GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e4m3_sat, bfloat16_to_float8_e4m3, true,\n+ uint16_t)\n+GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e5m2_sat, bfloat16_to_float8_e5m2, true,\n+ uint16_t)\n+\n+/* F32 -> E4M3/E5M2 conversions */\n+GEN_OCP_FP8_NARROW(vfncvt_f32_to_e4m3, float32_to_float8_e4m3, false, uint32_t)\n+GEN_OCP_FP8_NARROW(vfncvt_f32_to_e5m2, float32_to_float8_e5m2, false, uint32_t)\n+GEN_OCP_FP8_NARROW(vfncvt_f32_to_e4m3_sat, float32_to_float8_e4m3, true,\n+ uint32_t)\n+GEN_OCP_FP8_NARROW(vfncvt_f32_to_e5m2_sat, float32_to_float8_e5m2, true,\n+ uint32_t)\n+\n+/*\n+ * OCP FP8 Widening Conversions (FP8 -> BF16)\n+ * According to Zvfofp8min isa specification: \"No rounding occurs, and no\n+ * floating-point exception flags are set.\"\n+ * 1. Initialize a local float_status with no_signaling_nans=true\n+ * 2. Call the softfloat conversion function\n+ * 3. Intentionally DISCARD exception flags (not merged back)\n+ */\n+#define GEN_OCP_FP8_WIDEN(NAME, CONVERT_FN) \\\n+static uint16_t NAME(uint8_t a, float_status *s) \\\n+{ \\\n+ float_status local = *s; \\\n+ local.no_signaling_nans = true; \\\n+ return CONVERT_FN(a, &local); \\\n+}\n+\n+GEN_OCP_FP8_WIDEN(vfwcvt_e4m3_to_bf16, float8_e4m3_to_bfloat16)\n+GEN_OCP_FP8_WIDEN(vfwcvt_e5m2_to_bf16, float8_e5m2_to_bfloat16)\n+\n+/* vfwcvtbf16.f.f.w vd, vs2, vm # Convert OFP8 to BF16. */\n+RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e4m3, WOP_UU_B, H2, H1,\n+ vfwcvt_e4m3_to_bf16)\n+RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e5m2, WOP_UU_B, H2, H1,\n+ vfwcvt_e5m2_to_bf16)\n+GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e4m3, 2)\n+GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e5m2, 2)\n+\n+/* vfncvtbf16.f.f.w vd, vs2, vm # Convert BF16 to OFP8 without saturation. */\n+RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2,\n+ vfncvt_bf16_to_e4m3)\n+RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2,\n+ vfncvt_bf16_to_e5m2)\n+GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e4m3, 1)\n+GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e5m2, 1)\n+\n+/* vfncvtbf16.sat.f.f.w vd, vs2, vm # Convert BF16 to OFP8 with saturation. */\n+RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2,\n+ vfncvt_bf16_to_e4m3_sat)\n+RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2,\n+ vfncvt_bf16_to_e5m2_sat)\n+GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e4m3, 1)\n+GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e5m2, 1)\n+\n+/* Quad-width narrowing type for FP32 to OFP8 */\n+#define QOP_UU_B uint8_t, uint32_t, uint32_t\n+\n+/* vfncvt.f.f.q vd, vs2, vm # Convert FP32 to OFP8. */\n+RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4,\n+ vfncvt_f32_to_e4m3)\n+RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4,\n+ vfncvt_f32_to_e5m2)\n+GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e4m3, 1)\n+GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e5m2, 1)\n+\n+/* vfncvt.sat.f.f.q vd, vs2, vm # Convert FP32 to OFP8 with saturation. */\n+RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4,\n+ vfncvt_f32_to_e4m3_sat)\n+RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4,\n+ vfncvt_f32_to_e5m2_sat)\n+GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e4m3, 1)\n+GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e5m2, 1)\n+\n /*\n * Vector Reduction Operations\n */\n", "prefixes": [ "v5", "4/9" ] }