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GET /api/1.1/patches/2228594/?format=api
{ "id": 2228594, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228594/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-3-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427060928.2322570-3-max.chou@sifive.com>", "date": "2026-04-27T06:09:21", "name": "[v5,2/9] target/riscv: Add cfg property for Zvfofp8min extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2d64952a4d7683358d14f5527a66bde847931d9c", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/1.1/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260427060928.2322570-3-max.chou@sifive.com/mbox/", "series": [ { "id": 501579, "url": "http://patchwork.ozlabs.org/api/1.1/series/501579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501579", "date": "2026-04-27T06:09:19", "name": "target/riscv: Add RISC-V Zvfofp8min extension support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228594/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228594/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=eZHfyCnr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "According to the ISA spec of Zvfofp8min extension,\n\n\"The Zvfofp8min extension requires on the Zve32f extension.\"\n\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/cpu.c | 1 +\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n target/riscv/tcg/tcg-cpu.c | 5 +++++\n target/riscv/vector_helper.c | 3 ++-\n 4 files changed, 9 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex ce15a17c37..855c6bd4a9 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),\n ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),\n ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),\n+ ISA_EXT_DATA_ENTRY(zvfofp8min, PRIV_VERSION_1_12_0, ext_zvfofp8min),\n ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),\n ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),\n ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex 734fa079f2..f9cd79bae0 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -105,6 +105,7 @@ BOOL_FIELD(ext_zvfbfmin)\n BOOL_FIELD(ext_zvfbfwma)\n BOOL_FIELD(ext_zvfh)\n BOOL_FIELD(ext_zvfhmin)\n+BOOL_FIELD(ext_zvfofp8min)\n BOOL_FIELD(ext_smaia)\n BOOL_FIELD(ext_ssaia)\n BOOL_FIELD(ext_smctr)\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f7808895..40e7c72976 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -710,6 +710,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n return;\n }\n \n+ if (cpu->cfg.ext_zvfofp8min && !cpu->cfg.ext_zve32f) {\n+ error_setg(errp, \"Zvfofp8min extension depends on Zve32f extension\");\n+ return;\n+ }\n+\n if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {\n error_setg(errp, \"Zvfh extensions requires Zfhmin extension\");\n return;\ndiff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\nindex 60e2d42301..73437c1d20 100644\n--- a/target/riscv/vector_helper.c\n+++ b/target/riscv/vector_helper.c\n@@ -38,7 +38,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)\n int xlen = riscv_cpu_xlen(env);\n target_ulong reserved = 0;\n \n- if (riscv_cpu_cfg(env)->ext_zvfbfa) {\n+ if (riscv_cpu_cfg(env)->ext_zvfbfa ||\n+ riscv_cpu_cfg(env)->ext_zvfofp8min) {\n reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n } else {\n", "prefixes": [ "v5", "2/9" ] }