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GET /api/1.1/patches/2228585/?format=api
{ "id": 2228585, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228585/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1a8cf5e88051ab5c10417edb94df598ecbc810cf.1777269009.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<1a8cf5e88051ab5c10417edb94df598ecbc810cf.1777269009.git.nicolinc@nvidia.com>", "date": "2026-04-27T05:54:01", "name": "[v4,2/3] PCI: Allow ATS to be always on for pre-CXL devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a0e0752f1714336f68dbbd900c61af4f577b4bb6", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/1.1/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1a8cf5e88051ab5c10417edb94df598ecbc810cf.1777269009.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 501574, "url": "http://patchwork.ozlabs.org/api/1.1/series/501574/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501574", "date": "2026-04-27T05:53:59", "name": "Allow ATS to be always on for certain ATS-capable devices", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/501574/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228585/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228585/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53202-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=BM7C+AsH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "<jgg@nvidia.com>, <will@kernel.org>, <robin.murphy@arm.com>,\n\t<bhelgaas@google.com>", "CC": "<joro@8bytes.org>, <praan@google.com>, <baolu.lu@linux.intel.com>,\n\t<kevin.tian@intel.com>, <miko.lenczewski@arm.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,\n\t<vsethi@nvidia.com>, <linux-cxl@vger.kernel.org>, <nirmoyd@nvidia.com>", "Subject": "[PATCH v4 2/3] PCI: Allow ATS to be always on for pre-CXL devices", "Date": "Sun, 26 Apr 2026 22:54:01 -0700", "Message-ID": "\n <1a8cf5e88051ab5c10417edb94df598ecbc810cf.1777269009.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1777269009.git.nicolinc@nvidia.com>", "References": "<cover.1777269009.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN2PEPF000044AA:EE_|BY5PR12MB4082:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b27e9ad7-7561-4714-7327-08dea42174e0", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tDG8gDeSwyS/7zOpaeCYcKImjgGz3SjjUtmc5GG+f9QeefwZp0ab/+LbtUFuiEfmYVsOVU/JDPxm1FDSYejiCoe5kvonf9ZFiO8jU9MDPpZCNtVDFX30c3BXTVJK+jl5ePycnhFLNlnpBeKyoNUTfCPk3+QAnXJBD+csrrF9xOW+0O89JAYwi05eCIoOf+tpLTewa4fzJELk3kJJFa9SUTEbR179wKWVZKMLae37LDha6uEZiQLXCM9Ftp5wZNikmImp9DjLlCV0c/7fLQjv6GqAUW70/hkeHJRl8iHUl98PqhNE9ZzWxDvB2Easj09dyQAOqtbz5xk8yjwQGCYqizjRdTlkHcvazvAVNlzLZ3UMTBmAWBtWMbnwmkOWJseI3M7sOlwke3rQQMpHUFf9j5/GDIQzy3SvLM4u8tJX4MbnWZkcRgsshfDqBNl3mlTgOna138S/nXOz6UP9vbJ1KsR17GfRdH1cKjLb2gIjRKrL4IFR9mlYF+xVNm4ioksEXheTgJHxig5qiePZVFlfD9OXSwTD8IhgTeMv7uhLeD+OJ6JtipgVHEmN/dhqmjuH4kmgVcsnhVfusQn2LqFUf0P9vbuN4WQgjY5ckjaVaJKnGVrhBWjXz/zm0JGoP7jjOpaG38jYeuOsyEM4IFU33xNiKHVAZBO7+tWvQfuNjNTMrigXDSw5o3akVHXDUWM8KOadZf0qm5ndmE4XPs1l6SpSdunsSXbT2pwt2BnNJY2VCvJB1QRdM7VsvYEAZEKv883avt+/XO6qU4n08xo8T7A==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(7416014)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tnDZJ3/ngw7brZAKdWNVrMJS4v5Uin33Yx2tTpBt0QVOpNMOpaq3Hdm23v6B9fG7/FCaI3apuFNMoCGxZ76eG6utskQRWktumhRXczeFozkKdPkePhWc/B2E73pCkB5yYgzrrl5gyexAp8iK+pk9bwr4WFD0/zrv5kyVXUDxbKqWhhBisWrjb9stxC4RuXOzdLd+D5Lx2fiN4jfbQZCAuwVoJmho5AolC1sdSzCWSQrO4SBp+1Z0cFR1dcCRcqs+Ms/c86xWEUR45i1VN/u03LLnjWpR2N5l4JDkyWub1t2V2mzxgYZAziegzVXidKOfXG/Hs5j8HcgB5W9ZEltlGc0854QJ3eLgLKgBS15i1SlEg7RvHXPqt2+avDuRyNDR6rdVR8AxyMBVdgWrqXPs1bGGCex95j9JiK8pTSBRCHcWgqhcu5fpxcQpitz/NB4oo", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 05:54:33.2959\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b27e9ad7-7561-4714-7327-08dea42174e0", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBN2PEPF000044AA.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4082" }, "content": "Some NVIDIA GPU/NIC devices, though they don't implement CXL config space,\nhave many CXL-like properties. Call this kind \"pre-CXL\".\n\nSimilar to CXL.cache capability, these pre-CXL devices also require the ATS\nfunction even when their RIDs are IOMMU bypassed, i.e. keep ATS \"always on\"\nv.s. \"on demand\" when a non-zero PASID line gets enabled in SVA use cases.\n\nIntroduce pci_dev_specific_ats_always_on() quirk function to scan a list of\nIDs for these devices. Then, include it in pci_ats_always_on().\n\nSuggested-by: Jason Gunthorpe <jgg@nvidia.com>\nReviewed-by: Nirmoy Das <nirmoyd@nvidia.com>\nTested-by: Nirmoy Das <nirmoyd@nvidia.com>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\nReviewed-by: Jason Gunthorpe <jgg@nvidia.com>\nReviewed-by: Kevin Tian <kevin.tian@intel.com>\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n drivers/pci/pci.h | 9 +++++++++\n drivers/pci/ats.c | 3 ++-\n drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++\n 3 files changed, 49 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 4a14f88e543a2..4e0077478cd7a 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -1155,6 +1155,15 @@ static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)\n }\n #endif\n \n+#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_PCI_ATS)\n+bool pci_dev_specific_ats_always_on(struct pci_dev *dev);\n+#else\n+static inline bool pci_dev_specific_ats_always_on(struct pci_dev *dev)\n+{\n+\treturn false;\n+}\n+#endif\n+\n #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)\n int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,\n \t\t\t struct resource *res);\ndiff --git a/drivers/pci/ats.c b/drivers/pci/ats.c\nindex fc871858b65bc..3846447ea322f 100644\n--- a/drivers/pci/ats.c\n+++ b/drivers/pci/ats.c\n@@ -244,7 +244,8 @@ bool pci_ats_always_on(struct pci_dev *pdev)\n \tif (pdev->is_virtfn)\n \t\tpdev = pci_physfn(pdev);\n \n-\treturn pci_cxl_ats_always_on(pdev);\n+\treturn pci_cxl_ats_always_on(pdev) ||\n+\t pci_dev_specific_ats_always_on(pdev);\n }\n EXPORT_SYMBOL_GPL(pci_ats_always_on);\n \ndiff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex caaed1a01dc02..887babba97cc7 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -5715,6 +5715,44 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);\n+\n+static bool quirk_nvidia_gpu_ats_always_on(struct pci_dev *pdev)\n+{\n+\tswitch (pdev->device) {\n+\tcase 0x2e00 ... 0x2e3f: /* GB20B */\n+\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+static const struct pci_dev_ats_always_on {\n+\tu16 vendor;\n+\tu16 device;\n+\tbool (*ats_always_on)(struct pci_dev *dev);\n+} pci_dev_ats_always_on[] = {\n+\t/* NVIDIA GPUs */\n+\t{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, quirk_nvidia_gpu_ats_always_on },\n+\t/* NVIDIA CX10 Family NVlink-C2C */\n+\t{ PCI_VENDOR_ID_MELLANOX, 0x2101, NULL },\n+\t{ 0 }\n+};\n+\n+/* Some pre-CXL devices require ATS when it is IOMMU-bypassed */\n+bool pci_dev_specific_ats_always_on(struct pci_dev *pdev)\n+{\n+\tconst struct pci_dev_ats_always_on *i;\n+\n+\tfor (i = pci_dev_ats_always_on; i->vendor; i++) {\n+\t\tif (i->vendor != pdev->vendor)\n+\t\t\tcontinue;\n+\t\tif (i->ats_always_on && i->ats_always_on(pdev))\n+\t\t\treturn true;\n+\t\tif (!i->ats_always_on && i->device == pdev->device)\n+\t\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n #endif /* CONFIG_PCI_ATS */\n \n /* Freescale PCIe doesn't support MSI in RC mode */\n", "prefixes": [ "v4", "2/3" ] }