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GET /api/1.1/patches/2228479/?format=api
{ "id": 2228479, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228479/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-75-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260426134002.865628-75-richard.henderson@linaro.org>", "date": "2026-04-26T13:39:51", "name": "[74/84] fpu: Return struct from parts{64,128}_muladd_scalbn", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "505f7de548835e430e7d57b72e32b1538b519497", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.1/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260426134002.865628-75-richard.henderson@linaro.org/mbox/", "series": [ { "id": 501533, "url": "http://patchwork.ozlabs.org/api/1.1/series/501533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501533", "date": "2026-04-26T13:38:37", "name": "fpu: Export some internals for targets", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501533/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228479/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228479/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=isfU3Vvv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3Sv531xvz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 26 Apr 2026 23:57:37 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wGzpi-0000Xl-DN; Sun, 26 Apr 2026 09:47:39 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wGzof-0006IO-SY\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:35 -0400", "from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wGzod-0001lZ-FI\n for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:33 -0400", "by mail-pl1-x62e.google.com with SMTP id\n d9443c01a7336-2b7d3ecc10dso14946895ad.2\n for <qemu-devel@nongnu.org>; Sun, 26 Apr 2026 06:46:31 -0700 (PDT)", "from stoup.. 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"<20260426134002.865628-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::62e;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "At the same time, export.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n include/fpu/softfloat-parts.h | 9 +++\n fpu/softfloat.c | 81 ++++++++++---------\n fpu/softfloat-parts.c.inc | 148 +++++++++++++++++-----------------\n 3 files changed, 122 insertions(+), 116 deletions(-)", "diff": "diff --git a/include/fpu/softfloat-parts.h b/include/fpu/softfloat-parts.h\nindex 5b71809541..6416495eac 100644\n--- a/include/fpu/softfloat-parts.h\n+++ b/include/fpu/softfloat-parts.h\n@@ -184,6 +184,15 @@ FloatParts64 parts64_div(const FloatParts64 *a, const FloatParts64 *b,\n FloatParts128 parts128_div(const FloatParts128 *a, const FloatParts128 *b,\n float_status *s);\n \n+FloatParts64 parts64_muladd_scalbn(const FloatParts64 *a,\n+ const FloatParts64 *b,\n+ const FloatParts64 *c,\n+ int scale, int flags, float_status *s);\n+FloatParts128 parts128_muladd_scalbn(const FloatParts128 *a,\n+ const FloatParts128 *b,\n+ const FloatParts128 *c,\n+ int scale, int flags, float_status *s);\n+\n void parts64_round_canonical(FloatParts64 *p, float_status *s,\n const FloatFmt *fmt);\n \ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 1423695a5a..959a82636b 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -1904,15 +1904,15 @@ float16_muladd_scalbn(float16 a, float16 b, float16 c,\n FloatParts64 pa = float16_unpack_canonical(a, status);\n FloatParts64 pb = float16_unpack_canonical(b, status);\n FloatParts64 pc = float16_unpack_canonical(c, status);\n- FloatParts64 *pr =\n- parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n+ FloatParts64 pr = parts64_muladd_scalbn(&pa, &pb, &pc,\n+ scale, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &float16_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &float16_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &float16_params);\n+ return pack_raw64(&pr, &float16_params);\n }\n \n float16 float16_muladd(float16 a, float16 b, float16 c,\n@@ -1928,14 +1928,15 @@ float32_muladd_scalbn(float32 a, float32 b, float32 c,\n FloatParts64 pa = float32_unpack_canonical(a, status);\n FloatParts64 pb = float32_unpack_canonical(b, status);\n FloatParts64 pc = float32_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n+ FloatParts64 pr = parts64_muladd_scalbn(&pa, &pb, &pc,\n+ scale, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &float32_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &float32_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &float32_params);\n+ return pack_raw64(&pr, &float32_params);\n }\n \n float64 QEMU_SOFTFLOAT_ATTR\n@@ -1945,14 +1946,15 @@ float64_muladd_scalbn(float64 a, float64 b, float64 c,\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n FloatParts64 pc = float64_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n+ FloatParts64 pr = parts64_muladd_scalbn(&pa, &pb, &pc,\n+ scale, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &float64_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &float64_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &float64_params);\n+ return pack_raw64(&pr, &float64_params);\n }\n \n static bool force_soft_fma;\n@@ -2102,14 +2104,14 @@ float64 float64r32_muladd(float64 a, float64 b, float64 c,\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n FloatParts64 pc = float64_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n+ FloatParts64 pr = parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &float32_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &float32_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return float64r32_pack_raw(pr);\n+ return float64r32_pack_raw(&pr);\n }\n \n bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,\n@@ -2118,14 +2120,14 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,\n FloatParts64 pa = bfloat16_unpack_canonical(a, status);\n FloatParts64 pb = bfloat16_unpack_canonical(b, status);\n FloatParts64 pc = bfloat16_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n+ FloatParts64 pr = parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &bfloat16_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &bfloat16_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &bfloat16_params);\n+ return pack_raw64(&pr, &bfloat16_params);\n }\n \n float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n@@ -2134,14 +2136,14 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n FloatParts128 pa = float128_unpack_canonical(a, status);\n FloatParts128 pb = float128_unpack_canonical(b, status);\n FloatParts128 pc = float128_unpack_canonical(c, status);\n- FloatParts128 *pr = parts128_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n+ FloatParts128 pr = parts128_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n \n /* Round before applying negate result. */\n- parts128_uncanon(pr, status, &float128_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts128_uncanon(&pr, status, &float128_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return float128_pack_raw(pr);\n+ return float128_pack_raw(&pr);\n }\n \n /*\n@@ -5113,7 +5115,7 @@ float32 float32_exp2(float32 a, float_status *status)\n rp = float64_unpack_canonical(float64_one, status);\n for (int i = 0; i < 15; i++) {\n tp = float64_unpack_canonical(float32_exp2_coefficients[i], status);\n- rp = *parts64_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status);\n+ rp = parts64_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status);\n xnp = *parts64_mul(&xnp, &xp, status);\n }\n \n@@ -5162,7 +5164,7 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n n->sign = a->sign ^ b->sign;\n *cc = 0;\n } else {\n- FloatParts64 *q, q_buf, *r_precise, r_precise_buf;\n+ FloatParts64 *q, q_buf, r_precise;\n int float_exception_flags = 0;\n bool is_q_smallish;\n uint32_t r_flags;\n@@ -5191,12 +5193,11 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n 0, status, fmt);\n \n /* Compute precise remainder */\n- r_precise_buf = *b;\n- r_precise = parts64_muladd_scalbn(&r_precise_buf, n, a, 0,\n+ r_precise = parts64_muladd_scalbn(b, n, a, 0,\n float_muladd_negate_product, status);\n \n /* Round remainder to the target format */\n- *r = *r_precise;\n+ *r = r_precise;\n status->float_exception_flags = 0;\n parts64_round_canonical(r, status, fmt);\n r_flags = status->float_exception_flags;\n@@ -5220,17 +5221,17 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n * toward zero) or incremented.\n */\n saved_r_sign = r->sign;\n- saved_r_precise_sign = r_precise->sign;\n+ saved_r_precise_sign = r_precise.sign;\n r->sign = false;\n- r_precise->sign = false;\n- if (parts64_compare(r, r_precise, status, true) <\n+ r_precise.sign = false;\n+ if (parts64_compare(r, &r_precise, status, true) <\n float_relation_equal) {\n *dxc = 0x8;\n } else {\n *dxc = 0xc;\n }\n r->sign = saved_r_sign;\n- r_precise->sign = saved_r_precise_sign;\n+ r_precise.sign = saved_r_precise_sign;\n }\n }\n }\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 82d59df406..ab773ed241 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -677,15 +677,15 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n * Requires A and C extracted into a double-sized structure to provide the\n * extra space for the widening multiply.\n */\n-static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n- FloatPartsN *c, int scale,\n- int flags, float_status *s)\n+FloatPartsN partsN(muladd_scalbn)(const FloatPartsN *a,\n+ const FloatPartsN *b,\n+ const FloatPartsN *c,\n+ int scale, int flags, float_status *s)\n {\n- int ab_mask, abc_mask;\n- FloatPartsW p_widen, c_widen;\n-\n- ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n- abc_mask = float_cmask(c->cls) | ab_mask;\n+ int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n+ int abc_mask = float_cmask(c->cls) | ab_mask;\n+ bool c_sign = c->sign ^ !!(flags & float_muladd_negate_c);\n+ bool p_sign = a->sign ^ b->sign ^ !!(flags & float_muladd_negate_product);\n \n /*\n * It is implementation-defined whether the cases of (0,inf,qnan)\n@@ -694,18 +694,7 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n * off to the target-specific pick-a-NaN routine.\n */\n if (unlikely(abc_mask & float_cmask_anynan)) {\n- *a = partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask);\n- return a;\n- }\n-\n- if (flags & float_muladd_negate_c) {\n- c->sign ^= 1;\n- }\n-\n- /* Compute the sign of the product into A. */\n- a->sign ^= b->sign;\n- if (flags & float_muladd_negate_product) {\n- a->sign ^= 1;\n+ return partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask);\n }\n \n if (unlikely(!cmask_is_only_normals(ab_mask))) {\n@@ -715,86 +704,93 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n }\n \n if (ab_mask & float_cmask_inf) {\n- if (c->cls == float_class_inf && a->sign != c->sign) {\n+ if (c->cls == float_class_inf && p_sign != c_sign) {\n float_raise(float_flag_invalid | float_flag_invalid_isi, s);\n goto d_nan;\n }\n- goto return_inf;\n+ record_denormals_used(abc_mask, s);\n+ return (FloatPartsN){ .sign = p_sign, .cls = float_class_inf };\n }\n \n- g_assert(ab_mask & float_cmask_zero);\n- if (is_anynorm(c->cls)) {\n- *a = *c;\n- goto return_normal;\n- }\n- if (c->cls == float_class_zero) {\n+ record_denormals_used(abc_mask, s);\n+\n+ assert(ab_mask & float_cmask_zero);\n+ switch (c->cls) {\n+ case float_class_normal:\n+ case float_class_denormal:\n+ {\n+ FloatPartsN r = *c;\n+ r.exp += scale;\n+ return r;\n+ }\n+\n+ case float_class_zero:\n if (flags & float_muladd_suppress_add_product_zero) {\n- a->sign = c->sign;\n- } else if (a->sign != c->sign) {\n+ /* return zero with new sign */\n+ } else if (p_sign != c_sign) {\n goto return_sub_zero;\n }\n- goto return_zero;\n+ goto return_zero_c;\n+\n+ case float_class_inf:\n+ goto return_inf_c;\n+\n+ default:\n+ g_assert_not_reached();\n }\n- g_assert(c->cls == float_class_inf);\n }\n \n+ record_denormals_used(abc_mask, s);\n+\n if (unlikely(c->cls == float_class_inf)) {\n- a->sign = c->sign;\n- goto return_inf;\n+ goto return_inf_c;\n }\n \n /* Perform the multiplication step. */\n- p_widen.sign = a->sign;\n- p_widen.exp = a->exp + b->exp + 1;\n- fracN(mulw)(&p_widen, a, b);\n- if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n- fracW(add)(&p_widen, &p_widen, &p_widen);\n- p_widen.exp -= 1;\n- }\n+ {\n+ FloatPartsW p_widen = { .sign = p_sign, .exp = a->exp + b->exp + 1 };\n \n- /* Perform the addition step. */\n- if (c->cls != float_class_zero) {\n- /* Zero-extend C to less significant bits. */\n- fracN(widen)(&c_widen, c);\n- c_widen.exp = c->exp;\n+ fracN(mulw)(&p_widen, a, b);\n+ if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n+ fracW(add)(&p_widen, &p_widen, &p_widen);\n+ p_widen.exp -= 1;\n+ }\n \n- if (a->sign == c->sign) {\n- partsW(add_normal)(&p_widen, &c_widen);\n- } else if (!partsW(sub_normal)(&p_widen, &c_widen)) {\n- goto return_sub_zero;\n+ /* Perform the addition step. */\n+ if (c->cls != float_class_zero) {\n+ /* Zero-extend C to less significant bits. */\n+ FloatPartsW c_widen = { .sign = c_sign, .exp = c->exp };\n+ fracN(widen)(&c_widen, c);\n+\n+ if (p_widen.sign == c_sign) {\n+ partsW(add_normal)(&p_widen, &c_widen);\n+ } else if (!partsW(sub_normal)(&p_widen, &c_widen)) {\n+ goto return_sub_zero;\n+ }\n+ }\n+\n+ /* Narrow with sticky bit, for proper rounding later. */\n+ {\n+ FloatPartsN r = {\n+ .sign = p_widen.sign,\n+ .exp = p_widen.exp + scale,\n+ .cls = float_class_normal,\n+ };\n+ fracN(truncjam)(&r, &p_widen);\n+ return r;\n }\n }\n \n- /* Narrow with sticky bit, for proper rounding later. */\n- fracN(truncjam)(a, &p_widen);\n- a->sign = p_widen.sign;\n- a->exp = p_widen.exp;\n-\n- return_normal:\n- a->exp += scale;\n- finish_sign:\n- /*\n- * All result types except for \"return the default NaN\n- * because this is an Invalid Operation\" go through here;\n- * this matches the set of cases where we consumed a\n- * denormal input.\n- */\n- record_denormals_used(abc_mask, s);\n- return a;\n+ return_inf_c:\n+ return (FloatPartsN){ .sign = c_sign, .cls = float_class_inf };\n \n return_sub_zero:\n- a->sign = s->float_rounding_mode == float_round_down;\n- return_zero:\n- a->cls = float_class_zero;\n- goto finish_sign;\n-\n- return_inf:\n- a->cls = float_class_inf;\n- goto finish_sign;\n+ c_sign = s->float_rounding_mode == float_round_down;\n+ return_zero_c:\n+ return (FloatPartsN){ .sign = c_sign, .cls = float_class_zero };\n \n d_nan:\n- *a = partsN(default_nan)(s);\n- return a;\n+ return partsN(default_nan)(s);\n }\n \n /*\n", "prefixes": [ "74/84" ] }