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GET /api/1.1/patches/2228293/?format=api
{ "id": 2228293, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228293/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260423-add-ethernet-support-for-genio-520-720-v1-7-47ca918e0017@baylibre.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260423-add-ethernet-support-for-genio-520-720-v1-7-47ca918e0017@baylibre.com>", "date": "2026-04-23T13:25:58", "name": "[7/9] net: dwc_eth_qos: Add mediatek support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4b9cc2ed6730d5529606806d48768dea2e99b6c4", "submitter": { "id": 84831, "url": "http://patchwork.ozlabs.org/api/1.1/people/84831/?format=api", "name": "Julien Stephan", "email": "jstephan@baylibre.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260423-add-ethernet-support-for-genio-520-720-v1-7-47ca918e0017@baylibre.com/mbox/", "series": [ { "id": 501460, "url": "http://patchwork.ozlabs.org/api/1.1/series/501460/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501460", "date": "2026-04-23T13:25:57", "name": "Add ethernet support for genio 520/720 EVK boards", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501460/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228293/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228293/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20251104.gappssmtp.com\n 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(PDT)", "From": "Julien Stephan <jstephan@baylibre.com>", "Date": "Thu, 23 Apr 2026 15:25:58 +0200", "Subject": "[PATCH 7/9] net: dwc_eth_qos: Add mediatek support", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260423-add-ethernet-support-for-genio-520-720-v1-7-47ca918e0017@baylibre.com>", "References": "\n <20260423-add-ethernet-support-for-genio-520-720-v1-0-47ca918e0017@baylibre.com>", "In-Reply-To": "\n <20260423-add-ethernet-support-for-genio-520-720-v1-0-47ca918e0017@baylibre.com>", "To": "u-boot@lists.denx.de", "Cc": "GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Jerome Forissier <jerome.forissier@arm.com>, Tom Rini <trini@konsulko.com>,\n Christian Marangi <ansuelsmth@gmail.com>,\n Robert Marko <robert.marko@sartura.hr>, Simon Glass <sjg@chromium.org>,\n Yao Zi <me@ziyao.cc>, Quentin Schulz <quentin.schulz@cherry.de>,\n Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n \"Lucien.Jheng\" <lucienzx159@gmail.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Romain Gantois <romain.gantois@bootlin.com>,\n Siddharth Vadapalli <s-vadapalli@ti.com>,\n Yanqing Wang <ot_yanqing.wang@mediatek.com>, Beiyan Yun <root@infi.wang>,\n Ryder Lee <ryder.lee@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n David Lechner <dlechner@baylibre.com>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Kory Maincent <kory.maincent@bootlin.com>,\n Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Kuan-Wei Chiu <visitorckw@gmail.com>,\n Raymond Mao <raymond.mao@riscstar.com>, Peng Fan <peng.fan@nxp.com>,\n Stefan Roese <stefan.roese@mailbox.org>,\n Philip Molloy <philip.molloy@analog.com>,\n fanyi zhang <fanyi.zhang@mediatek.com>, Jonas Karlman <jonas@kwiboo.se>,\n Kever Yang <kever.yang@rock-chips.com>,\n Marek Vasut <marek.vasut@mailbox.org>,\n Patrick Delaunay <patrick.delaunay@foss.st.com>,\n Heiko Stuebner <heiko@sntech.de>,\n Samuel Holland <samuel.holland@sifive.com>,\n Christophe Roullier <christophe.roullier@foss.st.com>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Chris-QJ Chen <chris-qj.chen@mediatek.com>,\n Macpaul Lin <macpaul.lin@mediatek.com>,\n Sam Protsenko <semen.protsenko@linaro.org>,\n Michael Trimarchi <michael@amarulasolutions.com>,\n Sky Huang <SkyLake.Huang@mediatek.com>,\n Leo Yu-Chi Liang <ycliang@andestech.com>,\n Tommy Shih <tommy.shih@airoha.com>,\n Kevin-KW Huang <kevin-kw.huang@airoha.com>,\n Julien Stephan <jstephan@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Mailman-Approved-At": "Sat, 25 Apr 2026 22:36:28 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Synopsys DWC Ethernet QOS device support for MediaTek SoCs.\nin particular this initial commit adds support for Genio 520/720 and\nGenio 510/700 EVKs\n\nSigned-off-by: fanyi zhang <fanyi.zhang@mediatek.com>\nSigned-off-by: Julien Stephan <jstephan@baylibre.com>\n---\n MAINTAINERS | 1 +\n drivers/net/Kconfig | 7 +\n drivers/net/Makefile | 1 +\n drivers/net/dwc_eth_qos.c | 6 +\n drivers/net/dwc_eth_qos.h | 2 +\n drivers/net/dwc_eth_qos_mtk.c | 447 ++++++++++++++++++++++++++++++++++++++++++\n 6 files changed, 464 insertions(+)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex a59342de3e7..b62f77735f3 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -437,6 +437,7 @@ F:\tdrivers/clk/mediatek/\n F:\tdrivers/cpu/mtk_cpu.c\n F:\tdrivers/i2c/mtk_i2c.c\n F:\tdrivers/mmc/mtk-sd.c\n+F:\tdrivers/net/dwc_eth_qos_mtk.c\n F:\tdrivers/net/mtk_eth/\n F:\tdrivers/net/phy/mediatek/\n F:\tdrivers/phy/phy-mtk-*\ndiff --git a/drivers/net/Kconfig b/drivers/net/Kconfig\nindex 81d6e7cc2b1..c73be2ff1da 100644\n--- a/drivers/net/Kconfig\n+++ b/drivers/net/Kconfig\n@@ -246,6 +246,13 @@ config DWC_ETH_QOS_INTEL\n \t The Synopsys Designware Ethernet QOS IP block with the specific\n \t configuration used in the Intel Elkhart-Lake soc.\n \n+config DWC_ETH_QOS_MTK\n+\tbool \"Synopsys DWC Ethernet QOS device support for MediaTek SoCs\"\n+\tdepends on DWC_ETH_QOS && ARCH_MEDIATEK\n+\thelp\n+\t The Synopsys Designware Ethernet QOS IP block with the specific\n+\t configuration used in MediaTek SoCs.\n+\n config DWC_ETH_QOS_QCOM\n \tbool \"Synopsys DWC Ethernet QOS device support for Qcom SoCs\"\n \tdepends on DWC_ETH_QOS\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex c485068e5d2..761f7f0f451 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -21,6 +21,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o\n obj-$(CONFIG_DWC_ETH_QOS_ADI) += dwc_eth_qos_adi.o\n obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o\n obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o\n+obj-$(CONFIG_DWC_ETH_QOS_MTK) += dwc_eth_qos_mtk.o\n obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o\n obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o\n obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o\ndiff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c\nindex 0f31d646845..b7e6299c307 100644\n--- a/drivers/net/dwc_eth_qos.c\n+++ b/drivers/net/dwc_eth_qos.c\n@@ -1658,6 +1658,12 @@ static const struct udevice_id eqos_ids[] = {\n \t\t.compatible = \"adi,sc59x-dwmac-eqos\",\n \t\t.data = (ulong)&eqos_adi_config\n \t},\n+#endif\n+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_MTK)\n+\t{\n+\t\t.compatible = \"mediatek,mt8189-gmac\",\n+\t\t.data = (ulong)&eqos_mtk_config\n+\t},\n #endif\n \t{ }\n };\ndiff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h\nindex ba16f1a37cb..978b848b46e 100644\n--- a/drivers/net/dwc_eth_qos.h\n+++ b/drivers/net/dwc_eth_qos.h\n@@ -97,6 +97,7 @@ struct eqos_mac_regs {\n #define EQOS_MAC_MDIO_ADDRESS_PA_MASK\t\t\tGENMASK(25, 21)\n #define EQOS_MAC_MDIO_ADDRESS_RDA_MASK\t\t\tGENMASK(20, 16)\n #define EQOS_MAC_MDIO_ADDRESS_CR_MASK\t\t\tGENMASK(11, 8)\n+#define EQOS_MAC_MDIO_ADDRESS_CR_60_100\t\t\t0\n #define EQOS_MAC_MDIO_ADDRESS_CR_100_150\t\t1\n #define EQOS_MAC_MDIO_ADDRESS_CR_20_35\t\t\t2\n #define EQOS_MAC_MDIO_ADDRESS_CR_150_250\t\t4\n@@ -316,3 +317,4 @@ extern struct eqos_config eqos_stm32mp15_config;\n extern struct eqos_config eqos_stm32mp25_config;\n extern struct eqos_config eqos_jh7110_config;\n extern struct eqos_config eqos_adi_config;\n+extern struct eqos_config eqos_mtk_config;\ndiff --git a/drivers/net/dwc_eth_qos_mtk.c b/drivers/net/dwc_eth_qos_mtk.c\nnew file mode 100644\nindex 00000000000..275f1f2cf15\n--- /dev/null\n+++ b/drivers/net/dwc_eth_qos_mtk.c\n@@ -0,0 +1,447 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2026 BayLibre, SAS.\n+ * Author: Julien Stephan <jstephan@baylibre.com>\n+ */\n+\n+#include <dm.h>\n+#include <dm/device_compat.h>\n+#include <linux/bitfield.h>\n+#include <net.h>\n+#include <phy.h>\n+#include <regmap.h>\n+#include <syscon.h>\n+\n+#include \"dwc_eth_qos.h\"\n+\n+/*\n+ * Peri Configuration register is SoC specific,\n+ * so add a SoC specific prefix.\n+ */\n+#define MT8189_PERI_ETH_CTRL0\t\t0x270\n+#define MT8189_PERI_ETH_CTRL1\t\t0x274\n+#define MT8189_PERI_ETH_CTRL2\t\t0x278\n+\n+#define EQOS_MTK_RMII_CLK_SRC_INTERNAL\tBIT(28)\n+#define EQOS_MTK_RMII_CLK_SRC_RXC\tBIT(27)\n+#define EQOS_MTK_ETH_INTF_SEL\t\tGENMASK(26, 24)\n+#define EQOS_MTK_PHY_INTF_MII\t\t0\n+#define EQOS_MTK_PHY_INTF_RGMII\t\t1\n+#define EQOS_MTK_PHY_INTF_RMII\t\t4\n+#define EQOS_MTK_RGMII_TXC_PHASE_CTRL\tBIT(22)\n+#define EQOS_MTK_EXT_PHY_MODE\t\tBIT(21)\n+#define EQOS_MTK_TXC_OUT_OP\t\tBIT(20)\n+#define EQOS_MTK_DLY_GTXC_INV\t\tBIT(12)\n+#define EQOS_MTK_DLY_GTXC_STAGE_FINE\tGENMASK(11, 6)\n+#define EQOS_MTK_DLY_GTXC_ENABLE\tBIT(5)\n+#define EQOS_MTK_DLY_GTXC_STAGES\tGENMASK(4, 0)\n+\n+#define EQOS_MTK_DLY_RXC_INV\t\tBIT(25)\n+#define EQOS_MTK_DLY_RXC_ENABLE\t\tBIT(18)\n+#define EQOS_MTK_DLY_RXC_STAGES\t\tGENMASK(17, 13)\n+#define EQOS_MTK_DLY_TXC_INV\t\tBIT(12)\n+#define EQOS_MTK_DLY_TXC_ENABLE\t\tBIT(5)\n+#define EQOS_MTK_DLY_TXC_STAGES\t\tGENMASK(4, 0)\n+\n+#define EQOS_MTK_DLY_RMII_RXC_INV\tBIT(25)\n+#define EQOS_MTK_DLY_RMII_RXC_ENABLE\tBIT(18)\n+#define EQOS_MTK_DLY_RMII_RXC_STAGES\tGENMASK(17, 13)\n+#define EQOS_MTK_DLY_RMII_TXC_INV\tBIT(12)\n+#define EQOS_MTK_DLY_RMII_TXC_ENABLE\tBIT(5)\n+#define EQOS_MTK_DLY_RMII_TXC_STAGES\tGENMASK(4, 0)\n+\n+#define RX_DELAY_MAX_PS\t\t\t9800\n+#define TX_DELAY_MAX_PS\t\t\t9800\n+\n+#define OUT_OP\t\t\t\ttrue\n+\n+struct eqos_mtk_priv {\n+\tstruct regmap *peri_regmap;\n+\tbool rmii_clk_from_mac;\n+\tbool rmii_rxc;\n+\tu32 tx_delay_ps_per_stage;\n+\tu32 rx_delay_ps_per_stage;\n+\tbool tx_inv;\n+\tbool rx_inv;\n+};\n+\n+static int mtk_clk_init(struct udevice *dev)\n+{\n+\tstruct eqos_priv *eqos = dev_get_priv(dev);\n+\tint ret;\n+\n+\tret = clk_get_by_name(dev, \"mac_main\", &eqos->clk_tx);\n+\tif (ret) {\n+\t\tdev_err(dev, \"clk_get_by_name(mac_main) failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_get_by_name(dev, \"ptp_ref\", &eqos->clk_ptp_ref);\n+\tif (ret) {\n+\t\tdev_err(dev, \"clk_get_by_name(ptp_ref) failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_set_delay(struct udevice *dev)\n+{\n+\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tstruct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata;\n+\tu32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;\n+\n+\tswitch (pdata->phy_interface) {\n+\tcase PHY_INTERFACE_MODE_MII:\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_ENABLE,\n+\t\t\t\t\t!!mtk_pdata->tx_delay_ps_per_stage);\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_STAGES, mtk_pdata->tx_delay_ps_per_stage);\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_INV, mtk_pdata->tx_inv);\n+\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE,\n+\t\t\t\t\t!!mtk_pdata->rx_delay_ps_per_stage);\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, mtk_pdata->rx_delay_ps_per_stage);\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, mtk_pdata->rx_inv);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RMII:\n+\t\tif (mtk_pdata->rmii_clk_from_mac) {\n+\t\t\t/* case 1: mac provides the rmii reference clock,\n+\t\t\t * and the clock output to TXC pin.\n+\t\t\t * The egress timing can be adjusted by RMII_TXC delay macro circuit.\n+\t\t\t * The ingress timing can be adjusted by RMII_RXC delay macro circuit.\n+\t\t\t */\n+\t\t\trmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_ENABLE,\n+\t\t\t\t\t\t !!mtk_pdata->tx_delay_ps_per_stage);\n+\t\t\trmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_STAGES,\n+\t\t\t\t\t\t mtk_pdata->tx_delay_ps_per_stage);\n+\t\t\trmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_INV,\n+\t\t\t\t\t\t mtk_pdata->tx_inv);\n+\n+\t\t\trmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_ENABLE,\n+\t\t\t\t\t\t !!mtk_pdata->rx_delay_ps_per_stage);\n+\t\t\trmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_STAGES,\n+\t\t\t\t\t\t mtk_pdata->rx_delay_ps_per_stage);\n+\t\t\trmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_INV,\n+\t\t\t\t\t\t mtk_pdata->rx_inv);\n+\t\t} else {\n+\t\t\t/* case 2: the rmii reference clock is from external phy,\n+\t\t\t * and the property \"rmii_rxc\" indicates which pin(TXC/RXC)\n+\t\t\t * the reference clk is connected to. The reference clock is a\n+\t\t\t * received signal, so rx_delay_ps_per_stage/rx_inv are used to indicate\n+\t\t\t * the reference clock timing adjustment\n+\t\t\t */\n+\t\t\tif (mtk_pdata->rmii_rxc) {\n+\t\t\t\t/* the rmii reference clock from outside is connected\n+\t\t\t\t * to RXC pin, the reference clock will be adjusted\n+\t\t\t\t * by RXC delay macro circuit.\n+\t\t\t\t */\n+\t\t\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE,\n+\t\t\t\t\t\t\t!!mtk_pdata->rx_delay_ps_per_stage);\n+\t\t\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES,\n+\t\t\t\t\t\t\tmtk_pdata->rx_delay_ps_per_stage);\n+\t\t\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV,\n+\t\t\t\t\t\t\tmtk_pdata->rx_inv);\n+\t\t\t} else {\n+\t\t\t\t/* the rmii reference clock from outside is connected\n+\t\t\t\t * to TXC pin, the reference clock will be adjusted\n+\t\t\t\t * by TXC delay macro circuit.\n+\t\t\t\t */\n+\t\t\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_ENABLE,\n+\t\t\t\t\t\t\t!!mtk_pdata->rx_delay_ps_per_stage);\n+\t\t\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_STAGES,\n+\t\t\t\t\t\t\tmtk_pdata->rx_delay_ps_per_stage);\n+\t\t\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_INV,\n+\t\t\t\t\t\t\tmtk_pdata->rx_inv);\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\tgtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_ENABLE,\n+\t\t\t\t\t !!mtk_pdata->tx_delay_ps_per_stage);\n+\t\tgtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_STAGES,\n+\t\t\t\t\t mtk_pdata->tx_delay_ps_per_stage);\n+\t\tgtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_INV, mtk_pdata->tx_inv);\n+\t\tgtxc_delay_val |= EQOS_MTK_DLY_GTXC_STAGE_FINE;\n+\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE,\n+\t\t\t\t\t!!mtk_pdata->rx_delay_ps_per_stage);\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, mtk_pdata->rx_delay_ps_per_stage);\n+\t\tdelay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, mtk_pdata->rx_inv);\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_err(\"%s: dev=%p phy interface not supported\\n\", __func__, dev);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tregmap_update_bits(mtk_pdata->peri_regmap,\n+\t\t\t MT8189_PERI_ETH_CTRL0,\n+\t\t\t EQOS_MTK_RGMII_TXC_PHASE_CTRL |\n+\t\t\t EQOS_MTK_DLY_GTXC_ENABLE |\n+\t\t\t EQOS_MTK_DLY_GTXC_INV |\n+\t\t\t EQOS_MTK_DLY_GTXC_STAGE_FINE |\n+\t\t\t EQOS_MTK_DLY_GTXC_STAGES,\n+\t\t\t gtxc_delay_val);\n+\tregmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL1, delay_val);\n+\tregmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL2, rmii_delay_val);\n+\n+\treturn 0;\n+}\n+\n+static int mtk_set_interface(struct udevice *dev)\n+{\n+\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tstruct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata;\n+\tint rmii_clk_from_mac = mtk_pdata->rmii_clk_from_mac ? EQOS_MTK_RMII_CLK_SRC_INTERNAL : 0;\n+\tint rmii_rxc = mtk_pdata->rmii_rxc ? EQOS_MTK_RMII_CLK_SRC_RXC : 0;\n+\tu32 intf_val = 0;\n+\n+\t/* select phy interface in top control domain */\n+\tswitch (pdata->phy_interface) {\n+\tcase PHY_INTERFACE_MODE_MII:\n+\t\tintf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_MII);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RMII:\n+\t\tintf_val |= (rmii_rxc | rmii_clk_from_mac);\n+\t\tintf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_RMII);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\tintf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_RGMII);\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_err(\"%s: dev=%p phy interface not supported\\n\", __func__, dev);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* only support external PHY */\n+\tintf_val |= EQOS_MTK_EXT_PHY_MODE;\n+\tif (OUT_OP)\n+\t\tintf_val |= EQOS_MTK_TXC_OUT_OP;\n+\n+\tregmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL0, intf_val);\n+\n+\treturn 0;\n+}\n+\n+static int mtk_config_dt(struct udevice *dev)\n+{\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tstruct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata;\n+\tstruct ofnode_phandle_args args;\n+\tu32 tx_delay_ps, rx_delay_ps;\n+\tint ret;\n+\n+\tif (!dev_read_u32(dev, \"mediatek,tx-delay-ps\", &tx_delay_ps)) {\n+\t\tif (tx_delay_ps > TX_DELAY_MAX_PS) {\n+\t\t\tpr_err(\"%s: dev=%p Invalid TX clock delay: %dps\\n\",\n+\t\t\t __func__, dev, tx_delay_ps);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (!dev_read_u32(dev, \"mediatek,rx-delay-ps\", &rx_delay_ps)) {\n+\t\tif (rx_delay_ps > RX_DELAY_MAX_PS) {\n+\t\t\tpr_err(\"%s: dev=%p Invalid RX clock delay: %dps\\n\",\n+\t\t\t __func__, dev, rx_delay_ps);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* 290ps per stage */\n+\tmtk_pdata->tx_delay_ps_per_stage = tx_delay_ps / 290;\n+\tmtk_pdata->rx_delay_ps_per_stage = rx_delay_ps / 290;\n+\n+\tmtk_pdata->tx_inv = dev_read_bool(dev, \"mediatek,txc-inverse\");\n+\tmtk_pdata->rx_inv = dev_read_bool(dev, \"mediatek,rxc-inverse\");\n+\tmtk_pdata->rmii_clk_from_mac = dev_read_bool(dev, \"mediatek,rmii-clk-from-mac\");\n+\tmtk_pdata->rmii_rxc = dev_read_bool(dev, \"mediatek,rmii-rxc\");\n+\n+\tret = dev_read_phandle_with_args(dev, \"mediatek,pericfg\", NULL, 0, 0, &args);\n+\tif (ret) {\n+\t\tpr_err(\"Failed to get mediatek,pericfg property: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tmtk_pdata->peri_regmap = syscon_node_to_regmap(args.node);\n+\tif (IS_ERR(mtk_pdata->peri_regmap)) {\n+\t\tpr_err(\"%s: dev=%p Invalid perif_cfg reg\\n\", __func__, dev);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int eqos_probe_resources_mtk(struct udevice *dev)\n+{\n+\tstruct eqos_priv *eqos = dev_get_priv(dev);\n+\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tstruct eqos_mtk_priv *mtk_pdata;\n+\tint ret;\n+\n+\tdebug(\"%s(dev=%p):\\n\", __func__, dev);\n+\n+\tret = eqos_get_base_addr_dt(dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"eqos_get_base_addr_dt failed: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tmtk_pdata = calloc(1, sizeof(struct eqos_mtk_priv));\n+\tif (!mtk_pdata)\n+\t\treturn -ENOMEM;\n+\n+\tpdata->priv_pdata = mtk_pdata;\n+\n+\tret = mtk_config_dt(dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"mtk config dt failed: %d\\n\", ret);\n+\t\tgoto err;\n+\t}\n+\n+\tret = mtk_clk_init(dev);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tpdata->phy_interface = eqos->config->interface(dev);\n+\tif (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {\n+\t\tdev_err(dev, \"Invalid PHY interface\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto err;\n+\t}\n+\n+\tret = mtk_set_interface(dev);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tret = mtk_set_delay(dev);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tdebug(\"%s: OK\\n\", __func__);\n+\treturn 0;\n+err:\n+\tfree(mtk_pdata);\n+\treturn ret;\n+}\n+\n+static int eqos_remove_resources_mtk(struct udevice *dev)\n+{\n+\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tstruct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata;\n+\n+\tdebug(\"%s(dev=%p):\\n\", __func__, dev);\n+\n+\tfree(mtk_pdata);\n+\n+\tdebug(\"%s: OK\\n\", __func__);\n+\treturn 0;\n+}\n+\n+static int eqos_stop_clks_mtk(struct udevice *dev)\n+{\n+\tstruct eqos_priv *eqos = dev_get_priv(dev);\n+\n+\tdebug(\"%s(dev=%p):\\n\", __func__, dev);\n+\n+\tclk_disable(&eqos->clk_ptp_ref);\n+\tclk_disable(&eqos->clk_tx);\n+\n+\tdebug(\"%s: OK\\n\", __func__);\n+\treturn 0;\n+}\n+\n+static int eqos_start_clks_mtk(struct udevice *dev)\n+{\n+\tstruct eqos_priv *eqos = dev_get_priv(dev);\n+\tint ret;\n+\n+\tdebug(\"%s(dev=%p):\\n\", __func__, dev);\n+\n+\tret = clk_enable(&eqos->clk_tx);\n+\tif (ret < 0) {\n+\t\tpr_err(\"clk_enable(mac_main) failed: %d\", ret);\n+\t\tgoto err;\n+\t}\n+\n+\tret = clk_enable(&eqos->clk_ptp_ref);\n+\tif (ret < 0) {\n+\t\tpr_err(\"clk_enable(ptp_ref) failed: %d\", ret);\n+\t\tgoto err_disable_clk_mac_main;\n+\t}\n+\n+\tdebug(\"%s: OK\\n\", __func__);\n+\treturn 0;\n+\n+err_disable_clk_mac_main:\n+\tclk_disable(&eqos->clk_tx);\n+err:\n+\tdebug(\"%s: FAILED: %d\\n\", __func__, ret);\n+\treturn ret;\n+}\n+\n+static int eqos_fix_mac_speed_mtk(struct udevice *dev)\n+{\n+\tstruct eqos_priv *eqos = dev_get_priv(dev);\n+\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tstruct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata;\n+\n+\tdebug(\"%s(dev=%p):\\n\", __func__, dev);\n+\n+\tswitch (pdata->phy_interface) {\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\tif (eqos->phy->speed == SPEED_1000)\n+\t\t\tregmap_update_bits(mtk_pdata->peri_regmap,\n+\t\t\t\t\t MT8189_PERI_ETH_CTRL0,\n+\t\t\t\t\t EQOS_MTK_RGMII_TXC_PHASE_CTRL |\n+\t\t\t\t\t EQOS_MTK_DLY_GTXC_ENABLE |\n+\t\t\t\t\t EQOS_MTK_DLY_GTXC_INV |\n+\t\t\t\t\t EQOS_MTK_DLY_GTXC_STAGE_FINE |\n+\t\t\t\t\t EQOS_MTK_DLY_GTXC_STAGES,\n+\t\t\t\t\t EQOS_MTK_RGMII_TXC_PHASE_CTRL);\n+\t\telse\n+\t\t\tmtk_set_delay(dev);\n+\t\tbreak;\n+\tdefault:\n+\t\tdebug(\"%s: dev=%p no need to adjust mac delay\\n\", __func__, dev);\n+\t\tbreak;\n+\t}\n+\n+\tdebug(\"%s: OK\\n\", __func__);\n+\treturn 0;\n+}\n+\n+static struct eqos_ops eqos_mtk_ops = {\n+\t.eqos_inval_desc = eqos_inval_desc_generic,\n+\t.eqos_flush_desc = eqos_flush_desc_generic,\n+\t.eqos_inval_buffer = eqos_inval_buffer_generic,\n+\t.eqos_flush_buffer = eqos_flush_buffer_generic,\n+\t.eqos_probe_resources = eqos_probe_resources_mtk,\n+\t.eqos_remove_resources = eqos_remove_resources_mtk,\n+\t.eqos_stop_resets = eqos_null_ops,\n+\t.eqos_start_resets = eqos_null_ops,\n+\t.eqos_stop_clks = eqos_stop_clks_mtk,\n+\t.eqos_start_clks = eqos_start_clks_mtk,\n+\t.eqos_calibrate_pads = eqos_null_ops,\n+\t.eqos_disable_calibration = eqos_null_ops,\n+\t.eqos_set_tx_clk_speed = eqos_fix_mac_speed_mtk,\n+\t.eqos_get_enetaddr = eqos_null_ops,\n+};\n+\n+struct eqos_config eqos_mtk_config = {\n+\t.reg_access_always_ok = false,\n+\t.mdio_wait = 10000,\n+\t.swr_wait = 10,\n+\t.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,\n+\t.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_60_100,\n+\t.axi_bus_width = EQOS_AXI_WIDTH_64,\n+\t.interface = dev_read_phy_mode,\n+\t.ops = &eqos_mtk_ops\n+};\n", "prefixes": [ "7/9" ] }