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{ "id": 2228277, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228277/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/cd77957f-ee58-4080-a781-1cdfde60a494@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<cd77957f-ee58-4080-a781-1cdfde60a494@oss.qualcomm.com>", "date": "2026-04-25T19:21:35", "name": "[to-be-committed,RISC-V,PR,rtl-optimization/56096] Improve equality comparisons of a logical AND expressions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bf1da45bd7f9a8c1eec0385fff9b5d4b083787cb", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/cd77957f-ee58-4080-a781-1cdfde60a494@oss.qualcomm.com/mbox/", "series": [ { "id": 501481, "url": "http://patchwork.ozlabs.org/api/1.1/series/501481/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501481", "date": "2026-04-25T19:21:35", "name": "[to-be-committed,RISC-V,PR,rtl-optimization/56096] Improve equality comparisons of a logical AND expressions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501481/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228277/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228277/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=hMnPQvnB;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=TkFirg24;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------Jlbdm6oJudGGF07HXpeCXEYg\"", "Message-ID": "<cd77957f-ee58-4080-a781-1cdfde60a494@oss.qualcomm.com>", "Date": "Sat, 25 Apr 2026 13:21:35 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "Subject": "[to-be-committed][RISC-V][PR rtl-optimization/56096] Improve equality\n comparisons of a logical AND expressions", "X-Proofpoint-ORIG-GUID": "PZ9A2oJYsoz9V1wB2A0p5NKim9XUt9ph", "X-Authority-Analysis": "v=2.4 cv=Y5rIdBeN c=1 sm=1 tr=0 ts=69ed1443 cx=c_pps\n a=SvEPeNj+VMjHSW//kvnxuw==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=h7FgJG12TPv3PPeyIJ0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=h1YX4pn11c_3oJv6t7YA:9 a=B2y7HmGcmWMA:10 a=Kq8ClHjjuc5pcCNDwlU0:22", "X-Proofpoint-GUID": "PZ9A2oJYsoz9V1wB2A0p5NKim9XUt9ph", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI1MDIwMyBTYWx0ZWRfXyqfbuGOnMPdw\n at3j+i9fAVHKNfn74WkELSd0wzL+UV5qgFrGmioP3kQhHt5M8NbFwf4WHX7OQX1z18oT2XChi/I\n wska+BbHLMfP6PxPGEOxfd0yUNHqISBeWDI0lbzFJv6wVDKDqZld57/LDiGh3xbxeOnqCKf9cyp\n lNTuHCqLOWCbYMhmr+Hm8SkfliOei/TWfc9oszu/X0GhlO2h4tXk7TsfmELYIJ8VGWUymdYnR+i\n uOv91fbMdQB1PZZ1Fx6k/01YENZiCMviHY/QkF34OBAKFpFIWwV18AZtvqXSRVYeH/w/cJCAbbM\n WSncqj0lnKarqAw5ozq6YaeRyA8AKM0iJf/sOSkhWM9/TRhiPl92UdGZk0PhNqLt/Ve0e03iUvu\n K7/OLg9ex/vL5HqCs8x/YRixE5AAFwqRLuAerE3cUltYcLaZPvtdrYO8KM/tAVcaeAJ+llf8wzB\n /iPlCJf/Q8vODdPfAdg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-25_05,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501\n lowpriorityscore=0 bulkscore=0 suspectscore=0 spamscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604250203", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This BZ shows that we can improve certain comparisons for RISC-V. In \nparticular if we are testing the result of a logical AND for equality \nand one operand of the AND requires synthesis, we may be able to do \nbetter if we right shift away any trailing zeros from the constant and \nshift the other input as well. This wins when the shifted constant does \nnot require synthesis.\n\nThat may in turn allow improvement of a select of 0 and 2^n based on the \nzero/nonzero status of a logical AND. Essentially we can rewrite the \nsequence to remove a data dependency.\n\nConcretely:\n\n>\n> unsigned f1 (unsigned x, unsigned m)\n> {\n> x >>= ((m & 0x008080) ? 8 : 0);\n> return x;\n> }\n\nCompiles into:\n\n\n> li a5,32768\n> addi a5,a5,128\n> and a1,a1,a5\n> snez a1,a1\n> slliw a1,a1,3\n> srlw a0,a0,a1\n> ret\n\nBut after this patch we generate this instead:\n\n\n> srai a5,a1,7\n> andi a5,a5,257\n> li a4,8\n> czero.eqz a1,a4,a5\n> srlw a0,a0,a1\n> ret\n\nIt's just one less instruction, but the li can issue whenever the uarch \nwants before the srlw as it has no incoming dependency. So we're slight \nmore dense on encoding and slightly more efficient as well. Much like \n57650, I'm focused on the low level RISC-V codegen issues, not the \nbroader issues that are raised in the PR.\n\nThis has been in my tree for a while, so it's been tested on \nriscv32-elf, riscv64-elf and bootstrapped on the BPI which has support \nfor czero. Waiting on pre-commit CI before moving forward.\n\njeff", "diff": "diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 52f52c400cc7..c350283fa344 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -3201,6 +3201,62 @@ (define_insn_and_split \"zero_extendsidi2_shifted\"\n [(set_attr \"type\" \"shift\")\n (set_attr \"mode\" \"DI\")])\n \n+;; Handle logical AND feeding an equality test against zero where an operand\n+;; to the AND is a constant requiring synthesis. Because we only care about\n+;; zero/nonzero state afte the AND, we may be able to shift both operands\n+;; of the AND to the right and eliminate the need for constant synthesis.\n+;;\n+;; Once mvconst_internal goes away, this likely turns into a simple splitter.\n+(define_insn_and_split \"\"\n+ [(set (match_operand:X 0 \"register_operand\" \"=r\")\n+\t(any_eq:X (and:X (match_operand:X 1 \"register_operand\" \"r\")\n+\t\t\t (match_operand 2 \"shifted_const_arith_operand\"))\n+\t\t (const_int 0)))\n+ (clobber (match_scratch:X 3 \"=&r\"))]\n+ \"!SMALL_OPERAND (INTVAL (operands[2]))\"\n+ \"#\"\n+ \"&& reload_completed\"\n+ [(set (match_dup 3) (ashiftrt:X (match_dup 1) (match_dup 4)))\n+ (set (match_dup 3) (and:X (match_dup 3) (match_dup 2)))\n+ (set (match_dup 0) (any_eq:X (match_dup 3) (const_int 0)))]\n+{\n+ HOST_WIDE_INT shift = ctz_hwi (INTVAL (operands[2]));\n+ operands[4] = gen_int_mode (shift, QImode);\n+ operands[2] = gen_int_mode (INTVAL (operands[2]) >> shift, word_mode);\n+}\n+ [(set_attr \"type\" \"shift\")])\n+\n+;; The pattern above is a bridge to this pattern. Essentially a select\n+;; between 0 and 2^n based on the zero/nonzero status of the AND.\n+;;\n+;; It's no fewer instructions, but the resulting code has fewer data\n+;; dependencies and may compress better depending on 2^n.\n+(define_insn_and_split \"\"\n+ [(set (match_operand:X 0 \"register_operand\" \"=r\")\n+\t(ashift:X (any_eq:X\n+\t\t (and:X (match_operand:X 1 \"register_operand\" \"r\")\n+\t\t\t (match_operand 2 \"shifted_const_arith_operand\"))\n+\t\t (const_int 0))\n+\t\t (match_operand 3 \"const_int_operand\")))\n+ (clobber (match_scratch:X 4 \"=&r\"))\n+ (clobber (match_scratch:X 5 \"=&r\"))]\n+ \"TARGET_ZICOND && TARGET_ZBS\"\n+ \"#\"\n+ \"&& reload_completed\"\n+ [(set (match_dup 4) (ashiftrt:X (match_dup 1) (match_dup 6)))\n+ (set (match_dup 4) (and:X (match_dup 4) (match_dup 2)))\n+ (set (match_dup 5) (match_dup 3))\n+ (set (match_dup 0) (if_then_else:X (any_eq:X (match_dup 4) (const_int 0))\n+\t\t\t\t (match_dup 5)\n+\t\t\t\t (const_int 0)))]\n+{\n+ HOST_WIDE_INT shift = ctz_hwi (INTVAL (operands[2]));\n+ operands[3] = gen_int_mode (HOST_WIDE_INT_1U << INTVAL (operands[3]), word_mode);\n+ operands[6] = gen_int_mode (shift, QImode);\n+ operands[2] = gen_int_mode (INTVAL (operands[2]) >> shift, word_mode);\n+}\n+ [(set_attr \"type\" \"shift\")])\n+\n ;;\n ;; ....................\n ;;\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr56096.c b/gcc/testsuite/gcc.target/riscv/pr56096.c\nnew file mode 100644\nindex 000000000000..76ccd0b03ce9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr56096.c\n@@ -0,0 +1,19 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gcb_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+unsigned f1 (unsigned x, unsigned m)\n+{\n+ x >>= ((m & 0x008080) ? 8 : 0);\n+ return x;\n+}\n+\n+/* { dg-final { scan-assembler-not \"addi\\t\" } } */\n+/* { dg-final { scan-assembler-not \"and\\t\" } } */\n+/* { dg-final { scan-assembler-not \"snez\\t\" } } */\n+/* { dg-final { scan-assembler-not \"slli\\t\" } } */\n+/* { dg-final { scan-assembler-not \"slliw\\t\" } } */\n+/* { dg-final { scan-assembler-times \"srai\\t\" 1 } } */\n+/* { dg-final { scan-assembler-times \"andi\\t\" 1 } } */\n+/* { dg-final { scan-assembler-times \"czero\" 1 } } */\n", "prefixes": [ "to-be-committed", "RISC-V", "PR", "rtl-optimization/56096" ] }