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GET /api/1.1/patches/2228205/?format=api
{ "id": 2228205, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228205/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-1-07527be92e5d@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260425-imx8m-of-upstream-v1-1-07527be92e5d@nxp.com>", "date": "2026-04-25T00:36:53", "name": "[01/13] imx8mq: reform2: Switch to OF_UPSTREAM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "29ad6b1d71ececcc8824fc33d08be56b57baff6f", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/1.1/people/80723/?format=api", "name": "Peng Fan (OSS)", "email": "peng.fan@oss.nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-1-07527be92e5d@nxp.com/mbox/", "series": [ { "id": 501451, "url": "http://patchwork.ozlabs.org/api/1.1/series/501451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501451", "date": "2026-04-25T00:37:04", "name": "iMX8M: Covert to OF_UPSTREAM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501451/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228205/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228205/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=LHpiPE0M;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260425-imx8m-of-upstream-v1-1-07527be92e5d@nxp.com>", "References": "<20260425-imx8m-of-upstream-v1-0-07527be92e5d@nxp.com>", "In-Reply-To": "<20260425-imx8m-of-upstream-v1-0-07527be92e5d@nxp.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n kernel@puri.sm, u-boot@dh-electronics.com", "Cc": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Tom Rini <trini@konsulko.com>, \"Lukas F. Hartmann\" <lukas@mntre.com>,\n Patrick Wildt <patrick@blueri.se>, Ye Li <ye.li@nxp.com>,\n Frieder Schrempf <frieder.schrempf@kontron.de>,\n Benjamin Hahn <B.Hahn@phytec.de>, Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n Angus Ainslie <angus@akkea.ca>, Heiko Thiery <heiko.thiery@gmail.com>,\n Olaf Mandel <o.mandel@menlosystems.com>,\n Jagan Teki <jagan@amarulasolutions.com>,\n Matteo Lisi <matteo.lisi@engicam.com>,\n Manoj Sai <abbaraju.manojsai@amarulasolutions.com>,\n Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n Parth Pancholi <parth.pancholi@toradex.com>, Peng Fan <peng.fan@nxp.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "SI2PR01CA0020.apcprd01.prod.exchangelabs.com\n (2603:1096:4:192::6) To PAXPR04MB8459.eurprd04.prod.outlook.com\n (2603:10a6:102:1da::15)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": 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"X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b7a386b4-0d6f-4310-9489-08dea2581192", "X-MS-Exchange-CrossTenant-AuthSource": "PAXPR04MB8459.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Apr 2026 23:20:27.0312 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n Zil2vd7SssKB7Tbwjn3jwEfLnvbZut1QpcsP8twDbd2s6qDVQuOgM5idPi0pW69hHuNK8NJKR0+vgykcZiOZRw==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM8PR04MB7876", "X-OriginatorOrg": "oss.nxp.com", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Peng Fan <peng.fan@nxp.com>\n\narch/arm/dts/imx8mq-mnt-reform2.dts are almost same as upstream Linux\nimx8mq-mnt-reform2.dts, so switch to OF_USPTREAM for this board, with\nonly updating imx8mq-mnt-reform2-u-boot.dtsi to keep \"simple-panel\"\ncompatible string for display panel.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi | 4 +\n arch/arm/dts/imx8mq-mnt-reform2.dts | 354 ----------------------------\n arch/arm/dts/imx8mq-nitrogen-som.dtsi | 278 ----------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n configs/imx8mq_reform2_defconfig | 2 +-\n 6 files changed, 6 insertions(+), 634 deletions(-)", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex bff341d6118..68ca3b0ad02 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -879,7 +879,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mm-mx8menlo.dtb \\\n \timx8mm-phg.dtb \\\n \timx8mq-cm.dtb \\\n-\timx8mq-mnt-reform2.dtb \\\n \timx8mq-phanbell.dtb \\\n \timx8mp-data-modul-edm-sbc.dtb \\\n \timx8mp-dhcom-som-overlay-rev100.dtbo \\\ndiff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi\nindex 46a4dfe4e8a..71ce1b5b3ca 100644\n--- a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi\n+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi\n@@ -9,3 +9,7 @@\n &uart1 { /* console */\n \tbootph-pre-ram;\n };\n+\n+&{/panel} {\n+\tcompatible = \"innolux,n125hce-gn1\", \"simple-panel\";\n+};\ndiff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts\ndeleted file mode 100644\nindex 055031bba8c..00000000000\n--- a/arch/arm/dts/imx8mq-mnt-reform2.dts\n+++ /dev/null\n@@ -1,354 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-\n-/*\n- * Copyright 2019-2021 MNT Research GmbH\n- * Copyright 2021 Lucas Stach <dev@lynxeye.de>\n- */\n-\n-/dts-v1/;\n-\n-#include \"imx8mq-nitrogen-som.dtsi\"\n-\n-/ {\n-\tmodel = \"MNT Reform 2\";\n-\tcompatible = \"mntre,reform2\", \"boundary,imx8mq-nitrogen8m-som\", \"fsl,imx8mq\";\n-\tchassis-type = \"laptop\";\n-\n-\tbacklight: backlight {\n-\t\tcompatible = \"pwm-backlight\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_backlight>;\n-\t\tpwms = <&pwm2 0 10000 0>;\n-\t\tpower-supply = <®_main_usb>;\n-\t\tenable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;\n-\t\tbrightness-levels = <0 32 64 128 160 200 255>;\n-\t\tdefault-brightness-level = <6>;\n-\t};\n-\n-\tpanel {\n-\t\tcompatible = \"innolux,n125hce-gn1\", \"simple-panel\";\n-\t\tpower-supply = <®_main_3v3>;\n-\t\tbacklight = <&backlight>;\n-\t\tno-hpd;\n-\n-\t\tport {\n-\t\t\tpanel_in: endpoint {\n-\t\t\t\tremote-endpoint = <&edp_bridge_out>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tpcie1_refclk: clock-pcie1-refclk {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <100000000>;\n-\t};\n-\n-\treg_main_5v: regulator-main-5v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"5V\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t};\n-\n-\treg_main_3v3: regulator-main-3v3 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"3V3\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t};\n-\n-\treg_main_usb: regulator-main-usb {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"USB_PWR\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tvin-supply = <®_main_5v>;\n-\t};\n-\n-\treg_main_1v8: regulator-main-1v8 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"1V8\";\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tvin-supply = <®_main_3v3>;\n-\t};\n-\n-\treg_main_1v2: regulator-main-1v2 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"1V2\";\n-\t\tregulator-min-microvolt = <1200000>;\n-\t\tregulator-max-microvolt = <1200000>;\n-\t\tvin-supply = <®_main_5v>;\n-\t};\n-\n-\tsound {\n-\t\tcompatible = \"fsl,imx-audio-wm8960\";\n-\t\taudio-cpu = <&sai2>;\n-\t\taudio-codec = <&wm8960>;\n-\t\taudio-routing =\n-\t\t\t\"Headphone Jack\", \"HP_L\",\n-\t\t\t\"Headphone Jack\", \"HP_R\",\n-\t\t\t\"Ext Spk\", \"SPK_LP\",\n-\t\t\t\"Ext Spk\", \"SPK_LN\",\n-\t\t\t\"Ext Spk\", \"SPK_RP\",\n-\t\t\t\"Ext Spk\", \"SPK_RN\",\n-\t\t\t\"LINPUT1\", \"Mic Jack\",\n-\t\t\t\"Mic Jack\", \"MICB\",\n-\t\t\t\"LINPUT2\", \"Line In Jack\",\n-\t\t\t\"RINPUT2\", \"Line In Jack\";\n-\t\tmodel = \"wm8960-audio\";\n-\t};\n-};\n-\n-&dphy {\n-\tassigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;\n-\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;\n-\tassigned-clock-rates = <25000000>;\n-\tstatus = \"okay\";\n-};\n-\n-&fec1 {\n-\tstatus = \"okay\";\n-};\n-\n-&i2c3 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c3>;\n-\tstatus = \"okay\";\n-\n-\twm8960: codec@1a {\n-\t\tcompatible = \"wlf,wm8960\";\n-\t\treg = <0x1a>;\n-\t\tclocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;\n-\t\tclock-names = \"mclk\";\n-\t\t#sound-dai-cells = <0>;\n-\t};\n-\n-\trtc@68 {\n-\t\tcompatible = \"nxp,pcf8523\";\n-\t\treg = <0x68>;\n-\t};\n-};\n-\n-&i2c4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c4>;\n-\tclock-frequency = <400000>;\n-\tstatus = \"okay\";\n-\n-\tedp_bridge: bridge@2c {\n-\t\tcompatible = \"ti,sn65dsi86\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_edp_bridge>;\n-\t\treg = <0x2c>;\n-\t\tenable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;\n-\t\tvccio-supply = <®_main_1v8>;\n-\t\tvpll-supply = <®_main_1v8>;\n-\t\tvcca-supply = <®_main_1v2>;\n-\t\tvcc-supply = <®_main_1v2>;\n-\n-\t\tports {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tport@0 {\n-\t\t\t\treg = <0>;\n-\n-\t\t\t\tedp_bridge_in: endpoint {\n-\t\t\t\t\tremote-endpoint = <&mipi_dsi_out>;\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tport@1 {\n-\t\t\t\treg = <1>;\n-\n-\t\t\t\tedp_bridge_out: endpoint {\n-\t\t\t\t\tremote-endpoint = <&panel_in>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&lcdif {\n-\tassigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;\n-\tassigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;\n-\t/delete-property/assigned-clock-rates;\n-\tstatus = \"okay\";\n-};\n-\n-&mipi_dsi {\n-\tstatus = \"okay\";\n-\n-\tports {\n-\t\tport@1 {\n-\t\t\treg = <1>;\n-\n-\t\t\tmipi_dsi_out: endpoint {\n-\t\t\t\tremote-endpoint = <&edp_bridge_in>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&pcie1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_pcie1>;\n-\treset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;\n-\tclocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,\n-\t\t <&clk IMX8MQ_CLK_PCIE2_AUX>,\n-\t\t <&clk IMX8MQ_CLK_PCIE2_PHY>,\n-\t\t <&pcie1_refclk>;\n-\tclock-names = \"pcie\", \"pcie_aux\", \"pcie_phy\", \"pcie_bus\";\n-\tstatus = \"okay\";\n-};\n-\n-&pwm2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_pwm2>;\n-\tstatus = \"okay\";\n-};\n-\n-®_1p8v {\n-\tvin-supply = <®_main_5v>;\n-};\n-\n-®_snvs {\n-\tvin-supply = <®_main_5v>;\n-};\n-\n-®_arm_dram {\n-\tvin-supply = <®_main_5v>;\n-};\n-\n-®_dram_1p1v {\n-\tvin-supply = <®_main_5v>;\n-};\n-\n-®_soc_gpu_vpu {\n-\tvin-supply = <®_main_5v>;\n-};\n-\n-&sai2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_sai2>;\n-\tassigned-clocks = <&clk IMX8MQ_CLK_SAI2>;\n-\tassigned-clock-parents = <&clk IMX8MQ_CLK_25M>;\n-\tassigned-clock-rates = <25000000>;\n-\tfsl,sai-mclk-direction-output;\n-\tfsl,sai-asynchronous;\n-\tstatus = \"okay\";\n-};\n-\n-&snvs_rtc {\n-\tstatus = \"disabled\";\n-};\n-\n-&uart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy0 {\n-\tvbus-supply = <®_main_usb>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy1 {\n-\tvbus-supply = <®_main_usb>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_0 {\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_1 {\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc2 {\n-\tassigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;\n-\tassigned-clock-rates = <200000000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>;\n-\tvqmmc-supply = <®_main_3v3>;\n-\tvmmc-supply = <®_main_3v3>;\n-\tbus-width = <4>;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_backlight: backlightgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10\t\t0x3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_edp_bridge: edpbridgegrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20\t\t0x1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3: i2c3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL\t\t\t0x40000022\n-\t\t\tMX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA\t\t\t0x40000022\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4: i2c4grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL\t\t\t0x40000022\n-\t\t\tMX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA\t\t\t0x40000022\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pcie1: pcie1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23\t\t0x16\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pwm2: pwm2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT\t\t\t0x3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai2: sai2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0\t\t0xd6\n-\t\t\tMX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC\t\t0xd6\n-\t\t\tMX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK\t\t0xd6\n-\t\t\tMX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC\t\t0xd6\n-\t\t\tMX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK\t\t0xd6\n-\t\t\tMX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK\t\t0xd6\n-\t\t\tMX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0\t\t0xd6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX\t\t0x45\n-\t\t\tMX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX\t\t0x45\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B\t\t0x0\n-\t\t\tMX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0xc3\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi\ndeleted file mode 100644\nindex 395f77b5aca..00000000000\n--- a/arch/arm/dts/imx8mq-nitrogen-som.dtsi\n+++ /dev/null\n@@ -1,278 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2018 Boundary Devices\n- * Copyright 2021 Lucas Stach <dev@lynxeye.de>\n- */\n-\n-#include \"imx8mq.dtsi\"\n-\n-/ {\n-\tmodel = \"Boundary Devices i.MX8MQ Nitrogen8M\";\n-\tcompatible = \"boundary,imx8mq-nitrogen8m-som\", \"fsl,imx8mq\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart1;\n-\t};\n-\n-\treg_1p8v: regulator-fixed-1v8 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"1P8V\";\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-max-microvolt = <1800000>;\n-\t};\n-\n-\treg_snvs: regulator-fixed-snvs {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"VDD_SNVS\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t};\n-};\n-\n-&{/opp-table/opp-800000000} {\n-\topp-microvolt = <1000000>;\n-};\n-\n-&{/opp-table/opp-1000000000} {\n-\topp-microvolt = <1000000>;\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <®_arm_dram>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <®_arm_dram>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <®_arm_dram>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <®_arm_dram>;\n-};\n-\n-&fec1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec1>;\n-\tphy-mode = \"rgmii-id\";\n-\tphy-handle = <ðphy0>;\n-\tfsl,magic-packet;\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tethphy0: ethernet-phy@4 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <4>;\n-\t\t\tinterrupt-parent = <&gpio1>;\n-\t\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\treset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t\treset-deassert-us = <300>;\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tstatus = \"okay\";\n-\n-\ti2c-mux@70 {\n-\t\tcompatible = \"nxp,pca9546\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_i2c1_pca9546>;\n-\t\treg = <0x70>;\n-\t\treset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\ti2c1a: i2c@0 {\n-\t\t\treg = <0>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treg_arm_dram: regulator@60 {\n-\t\t\t\tcompatible = \"fcs,fan53555\";\n-\t\t\t\treg = <0x60>;\n-\t\t\t\tregulator-name = \"VDD_ARM_DRAM_1V\";\n-\t\t\t\tregulator-min-microvolt = <1000000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c1b: i2c@1 {\n-\t\t\treg = <1>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treg_dram_1p1v: regulator@60 {\n-\t\t\t\tcompatible = \"fcs,fan53555\";\n-\t\t\t\treg = <0x60>;\n-\t\t\t\tregulator-name = \"NVCC_DRAM_1P1V\";\n-\t\t\t\tregulator-min-microvolt = <1100000>;\n-\t\t\t\tregulator-max-microvolt = <1100000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c1c: i2c@2 {\n-\t\t\treg = <2>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treg_soc_gpu_vpu: regulator@60 {\n-\t\t\t\tcompatible = \"fcs,fan53555\";\n-\t\t\t\treg = <0x60>;\n-\t\t\t\tregulator-name = \"VDD_SOC_GPU_VPU\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <900000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c1d: i2c@3 {\n-\t\t\treg = <3>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t};\n-\t};\n-};\n-\n-&pgc_gpu {\n-\tpower-supply = <®_soc_gpu_vpu>;\n-};\n-\n-&pgc_vpu {\n-\tpower-supply = <®_soc_gpu_vpu>;\n-};\n-\n-&uart1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc1 {\n-\tassigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;\n-\tassigned-clock-rates = <400000000>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tvqmmc-supply = <®_1p8v>;\n-\tvmmc-supply = <®_snvs>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tno-mmc-hs400;\n-\tno-sdio;\n-\tno-sd;\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_wdog>;\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_fec1: fec1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_ENET_MDC_ENET1_MDC\t\t\t0x3\n-\t\t\tMX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO\t\t0x23\n-\t\t\tMX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t\t0xd1\n-\t\t\tMX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t\t0xd1\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9\t\t0x1\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11\t\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL\t\t\t0x40000022\n-\t\t\tMX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA\t\t\t0x40000022\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1_pca9546: i2c1-pca9546grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX\t\t0x45\n-\t\t\tMX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX\t\t0x45\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x83\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xc3\n-\t\t\tMX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x8d\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xcd\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xcd\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK\t\t\t0x9f\n-\t\t\tMX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD\t\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6\t\t0xdf\n-\t\t\tMX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7\t\t0xdf\n-\t\t>;\n-\t};\n-\n-\tpinctrl_wdog: wdoggrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B\t\t0xc6\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex 8b0d48b07b3..40b5de47cfb 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -84,6 +84,7 @@ config TARGET_IMX8MQ_REFORM2\n \tbool \"imx8mq_reform2\"\n \tselect IMX8MQ\n \tselect IMX8M_LPDDR4\n+\timply OF_UPSTREAM\n \n config TARGET_IMX8MM_DATA_MODUL_EDM_SBC\n \tbool \"Data Modul eDM SBC i.MX8M Mini\"\ndiff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig\nindex efa1b1ac1d5..fec20ed81d8 100644\n--- a/configs/imx8mq_reform2_defconfig\n+++ b/configs/imx8mq_reform2_defconfig\n@@ -11,7 +11,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y\n CONFIG_SYS_I2C_MXC_I2C2=y\n CONFIG_SYS_I2C_MXC_I2C3=y\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mq-mnt-reform2\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mq-mnt-reform2\"\n CONFIG_TARGET_IMX8MQ_REFORM2=y\n CONFIG_DM_RESET=y\n CONFIG_SYS_MONITOR_LEN=524288\n", "prefixes": [ "01/13" ] }