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GET /api/1.1/patches/2228201/?format=api
{ "id": 2228201, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-9-07527be92e5d@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260425-imx8m-of-upstream-v1-9-07527be92e5d@nxp.com>", "date": "2026-04-25T00:37:01", "name": "[09/13] imx8mm: data-modul-edm-sbc: Switch OF_UPSTREAM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "779b754c751bee60e698ef129fae8954c5c6f236", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/1.1/people/80723/?format=api", "name": "Peng Fan (OSS)", "email": "peng.fan@oss.nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-9-07527be92e5d@nxp.com/mbox/", "series": [ { "id": 501451, "url": "http://patchwork.ozlabs.org/api/1.1/series/501451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501451", "date": "2026-04-25T00:37:04", "name": "iMX8M: Covert to OF_UPSTREAM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501451/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228201/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228201/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=EKrNMMV8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260425-imx8m-of-upstream-v1-9-07527be92e5d@nxp.com>", "References": "<20260425-imx8m-of-upstream-v1-0-07527be92e5d@nxp.com>", "In-Reply-To": "<20260425-imx8m-of-upstream-v1-0-07527be92e5d@nxp.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n kernel@puri.sm, u-boot@dh-electronics.com", "Cc": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Tom Rini <trini@konsulko.com>, \"Lukas F. Hartmann\" <lukas@mntre.com>,\n Patrick Wildt <patrick@blueri.se>, Ye Li <ye.li@nxp.com>,\n Frieder Schrempf <frieder.schrempf@kontron.de>,\n Benjamin Hahn <B.Hahn@phytec.de>, Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n Angus Ainslie <angus@akkea.ca>, Heiko Thiery <heiko.thiery@gmail.com>,\n Olaf Mandel <o.mandel@menlosystems.com>,\n Jagan Teki <jagan@amarulasolutions.com>,\n Matteo Lisi <matteo.lisi@engicam.com>,\n Manoj Sai <abbaraju.manojsai@amarulasolutions.com>,\n Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n Parth Pancholi <parth.pancholi@toradex.com>, Peng Fan <peng.fan@nxp.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "SI2PR01CA0020.apcprd01.prod.exchangelabs.com\n (2603:1096:4:192::6) To PAXPR04MB8459.eurprd04.prod.outlook.com\n (2603:10a6:102:1da::15)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "\n PAXPR04MB8459:EE_|AM8PR04MB7876:EE_|PAXPR04MB8427:EE_|AMVPR04MB12628:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6a16fb36-82ca-4282-e5e8-08dea258304a", "X-MS-Exchange-SharedMailbox-RoutingAgent-Processed": "True", "X-LD-Processed": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|7416014|376014|52116014|1800799024|19092799006|366016|56012099003|18002099003|22082099003|38350700014;", "X-Microsoft-Antispam-Message-Info": "\n WRbu4y8y86tbR9EZe8RstPuedOMWU4CTNCPsf9lByAy9OrIuw6Fu5WiJpxzk5u2y8YNT5DxVOuQpOE6y8PoKijbvJ+Gjcbik5JYNCGpVGLFi7Fy0EMH/X61dEzEEGEwZR0Q5GUzSixzktJ2SVRwuRTGQjIOe7zQfcZyz5rrBo+zJd/6nFoScwnu8p57oVhL2Orvs3BcN4d9N2OWohX9o4NdtidkBX5Sd/qsPH6qd3+8/lnI2i8Ln7d8EJde1WdrhSD63S4OvcFM6GgbN1GPkLNRZW1Ta9Zamt/JtTkfTZviye+YKSdJvayNnAMkU58psPWubnn00FK6m5GdQJc8bVYcfiTDU+nR7wKYI696CUscUtelQ9M2pdqF52VQlqHmMIiuUOJ9MeFYUaU46hdn3nqakym2zAh+CXKtX2uBvaSM9T3kf/83fOxd8a/JMTGc4NYXFl+I4a46NAAwfZNIAGnTcE8XfgdAuPrwKz3bBfhiLNFdwYSQTBYNFCPK2sM+v/Krx0cYIbY4dcBPGZD4FHfolYMdN5SxLdtbD6jLr2BUjXRCFSsPbrh8qXdiau52OTy5IHM+1a42gqYpeyL3oov4mvHxI8vj7EMfJR8lgpYc0VZ2yvFAle4zHO6hnDcssVX7yL2xhv7Yjhw7m4zpdpuhrDd+XnkiOK6h4Vz2gR6jhjagpKmCLrAWb/41gKoHdEAXcYmm4EHfoY2nFa/RJaFmoJwBCRTDjMeUUAn9IVgzljpr7LLvQR9UzgKbdIELN57qJdB4kk/c0OL3mkht9TBv9N6zKTnx6NQ10dAWrWGc=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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So switch to OF_UPSTREAM by dropping the U-Boot\ncopy of the dts, enabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mm-data-modul-edm-sbc.dts | 997 ----------------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n board/data_modul/imx8mm_edm_sbc/MAINTAINERS | 1 -\n configs/imx8mm_data_modul_edm_sbc_defconfig | 2 +-\n 5 files changed, 2 insertions(+), 1000 deletions(-)", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex dff05dd5888..8656100fea2 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -873,7 +873,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \\\n \timx8-capricorn-cxg3.dtb \\\n \n dtb-$(CONFIG_ARCH_IMX8M) += \\\n-\timx8mm-data-modul-edm-sbc.dtb \\\n \timx8mm-icore-mx8mm-ctouch2.dtb \\\n \timx8mm-icore-mx8mm-edimm2.2.dtb \\\n \timx8mm-phg.dtb \\\ndiff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts\ndeleted file mode 100644\nindex 778bdbe228d..00000000000\n--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts\n+++ /dev/null\n@@ -1,997 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2022 Marek Vasut <marex@denx.de>\n- */\n-\n-/dts-v1/;\n-\n-#include <dt-bindings/net/qca-ar803x.h>\n-#include <dt-bindings/phy/phy-imx8-pcie.h>\n-#include \"imx8mm.dtsi\"\n-\n-/ {\n-\tmodel = \"Data Modul i.MX8M Mini eDM SBC\";\n-\tcompatible = \"dmo,imx8mm-data-modul-edm-sbc\", \"fsl,imx8mm\";\n-\n-\taliases {\n-\t\trtc0 = &rtc;\n-\t\trtc1 = &snvs_rtc;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = &uart3;\n-\t};\n-\n-\tmemory@40000000 {\n-\t\tdevice_type = \"memory\";\n-\t\t/* There are 1/2/4 GiB options, adjusted by bootloader. */\n-\t\treg = <0x0 0x40000000 0 0x40000000>;\n-\t};\n-\n-\tbacklight: backlight {\n-\t\tcompatible = \"pwm-backlight\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_panel_backlight>;\n-\t\tbrightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;\n-\t\tdefault-brightness-level = <7>;\n-\t\tenable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;\n-\t\tpwms = <&pwm1 0 5000000 0>;\n-\t\t/* Disabled by default, unless display board plugged in. */\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tclk_xtal25: clk-xtal25 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <25000000>;\n-\t};\n-\n-\tpanel: panel {\n-\t\tbacklight = <&backlight>;\n-\t\tpower-supply = <®_panel_vcc>;\n-\t\t/* Disabled by default, unless display board plugged in. */\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\treg_panel_vcc: regulator-panel-vcc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_panel_vcc_reg>;\n-\t\tregulator-name = \"PANEL_VCC\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tgpio = <&gpio3 6 0>;\n-\t\tenable-active-high;\n-\t\t/* Disabled by default, unless display board plugged in. */\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\treg_usdhc2_vcc: regulator-usdhc2-vcc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;\n-\t\tregulator-name = \"V_3V3_SD\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tgpio = <&gpio2 19 0>;\n-\t\tenable-active-high;\n-\t};\n-\n-\twatchdog-gpio {\n-\t\t/* TPS3813 */\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_watchdog_gpio>;\n-\t\tcompatible = \"linux,wdt-gpio\";\n-\t\talways-enabled;\n-\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n-\t\thw_algo = \"level\";\n-\t\t/* Reset triggers in 2..3 seconds */\n-\t\thw_margin_ms = <1500>;\n-\t\t/* Disabled by default */\n-\t\tstatus = \"disabled\";\n-\t};\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&ddrc {\n-\toperating-points-v2 = <&ddrc_opp_table>;\n-\n-\tddrc_opp_table: opp-table {\n-\t\tcompatible = \"operating-points-v2\";\n-\n-\t\topp-25M {\n-\t\t\topp-hz = /bits/ 64 <25000000>;\n-\t\t};\n-\n-\t\topp-100M {\n-\t\t\topp-hz = /bits/ 64 <100000000>;\n-\t\t};\n-\n-\t\topp-750M {\n-\t\t\topp-hz = /bits/ 64 <750000000>;\n-\t\t};\n-\t};\n-};\n-\n-&ecspi1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi1>;\n-\tcs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;\n-\tstatus = \"okay\";\n-\n-\tflash@0 {\t/* W25Q128FVSI */\n-\t\tcompatible = \"jedec,spi-nor\";\n-\t\tm25p,fast-read;\n-\t\tspi-max-frequency = <50000000>;\n-\t\treg = <0>;\n-\t};\n-};\n-\n-&ecspi2 {\t/* Feature connector SPI */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi2>;\n-\tcs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;\n-\t/* Disabled by default, unless feature board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-&ecspi3 {\t/* Display connector SPI */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi3>;\n-\tcs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;\n-\t/* Disabled by default, unless display board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-&fec1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec1>;\n-\tphy-mode = \"rgmii-id\";\n-\tphy-handle = <&fec1_phy>;\n-\tphy-supply = <&buck4_reg>;\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* Atheros AR8031 PHY */\n-\t\tfec1_phy: ethernet-phy@0 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <0>;\n-\t\t\t/*\n-\t\t\t * Dedicated ENET_WOL# signal is unused, the PHY\n-\t\t\t * can wake the SoC up via INT signal as well.\n-\t\t\t */\n-\t\t\tinterrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\treset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t\treset-deassert-us = <10000>;\n-\t\t\tqca,clk-out-frequency = <125000000>;\n-\t\t\tqca,clk-out-strength = <AR803X_STRENGTH_FULL>;\n-\t\t\tqca,keep-pll-enabled;\n-\t\t\tvddio-supply = <&vddio>;\n-\n-\t\t\tvddio: vddio-regulator {\n-\t\t\t\tregulator-name = \"VDDIO\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t};\n-\n-\t\t\tvddh: vddh-regulator {\n-\t\t\t\tregulator-name = \"VDDH\";\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"\", \"ENET_RST#\", \"WDOG_B#\", \"PMIC_INT#\",\n-\t\t\"\", \"M2-B_PCIE_RST#\", \"M2-B_PCIE_WAKE#\", \"RTC_IRQ#\",\n-\t\t\"WDOG_KICK#\", \"M2-B_PCIE_CLKREQ#\",\n-\t\t\"USB1_OTG_ID_3V3\", \"ENET_WOL#\",\n-\t\t\"\", \"\", \"\", \"ENET_INT#\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"MEMCFG2\", \"MEMCFG1\", \"DSI_RESET_1V8#\", \"DSI_IRQ_1V8#\",\n-\t\t\"M2-B_FULL_CARD_PWROFF_1V8#\", \"EEPROM_WP_1V8#\",\n-\t\t\"PCIE_CLK_GEN_CLKPWRGD_PD_1V8#\", \"GRAPHICS_PRSNT_1V8#\",\n-\t\t\"MEMCFG0\", \"WDOG_EN\",\n-\t\t\"M2-B_W_DISABLE1_WWAN_1V8#\", \"M2-B_W_DISABLE2_GPS_1V8#\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"SD2_RESET#\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names =\n-\t\t\"BL_ENABLE_1V8\", \"PG_V_IN_VAR#\", \"\", \"\",\n-\t\t\"\", \"\", \"TFT_ENABLE_1V8\", \"GRAPHICS_GPIO0_1V8\",\n-\t\t\"CSI_PD_1V8\", \"CSI_RESET_1V8#\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"M2-B_WAKE_WWAN_1V8#\",\n-\t\t\"M2-B_RESET_1V8#\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio4 {\n-\tgpio-line-names =\n-\t\t\"NC0\", \"NC1\", \"BOOTCFG0\", \"BOOTCFG1\",\n-\t\t\"BOOTCFG2\", \"BOOTCFG3\", \"BOOTCFG4\", \"BOOTCFG5\",\n-\t\t\"BOOTCFG6\", \"BOOTCFG7\", \"NC10\", \"NC11\",\n-\t\t\"BOOTCFG8\", \"BOOTCFG9\", \"BOOTCFG10\", \"BOOTCFG11\",\n-\t\t\"BOOTCFG12\", \"BOOTCFG13\", \"BOOTCFG14\", \"BOOTCFG15\",\n-\t\t\"NC20\", \"\", \"\", \"\",\n-\t\t\"\", \"CAN_INT#\", \"CAN_RST#\", \"GPIO4_IO27\",\n-\t\t\"DIS_USB_DN2\", \"\", \"\", \"\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names =\n-\t\t\"\", \"DIS_USB_DN1\", \"USBHUB_RESET#\", \"GPIO5_IO03\",\n-\t\t\"GPIO5_IO04\", \"\", \"\", \"\",\n-\t\t\"\", \"SPI1_CS#\", \"\", \"\",\n-\t\t\"\", \"SPI2_CS#\", \"I2C1_SCL_3V3\", \"I2C1_SDA_3V3\",\n-\t\t\"I2C2_SCL_3V3\", \"I2C2_SDA_3V3\", \"I2C3_SCL_3V3\", \"I2C3_SDA_3V3\",\n-\t\t\"I2C4_SCL_3V3\", \"I2C4_SDA_3V3\", \"\", \"\",\n-\t\t\"\", \"SPI3_CS#\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&i2c1 {\n-\t/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n-\tscl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\tpmic: pmic@4b {\n-\t\tcompatible = \"rohm,bd71847\";\n-\t\treg = <0x4b>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pmic>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <3 IRQ_TYPE_EDGE_FALLING>;\n-\t\trohm,reset-snvs-powered;\n-\n-\t\t/*\n-\t\t * i.MX 8M Mini Data Sheet for Consumer Products\n-\t\t * 3.1.3 Operating ranges\n-\t\t * MIMX8MM4DVTLZAA\n-\t\t */\n-\t\tregulators {\n-\t\t\t/* VDD_SOC */\n-\t\t\tbuck1_reg: BUCK1 {\n-\t\t\t\tregulator-name = \"buck1\";\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <850000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t};\n-\n-\t\t\t/* VDD_ARM */\n-\t\t\tbuck2_reg: BUCK2 {\n-\t\t\t\tregulator-name = \"buck2\";\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <1050000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t\trohm,dvs-run-voltage = <1000000>;\n-\t\t\t\trohm,dvs-idle-voltage = <950000>;\n-\t\t\t};\n-\n-\t\t\t/* VDD_DRAM, BUCK5 */\n-\t\t\tbuck3_reg: BUCK3 {\n-\t\t\t\tregulator-name = \"buck3\";\n-\t\t\t\t/* 1.5 GHz DDR bus clock */\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 3V3_VDD, BUCK6 */\n-\t\t\tbuck4_reg: BUCK4 {\n-\t\t\t\tregulator-name = \"buck4\";\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 1V8_VDD, BUCK7 */\n-\t\t\tbuck5_reg: BUCK5 {\n-\t\t\t\tregulator-name = \"buck5\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 1V1_NVCC_DRAM, BUCK8 */\n-\t\t\tbuck6_reg: BUCK6 {\n-\t\t\t\tregulator-name = \"buck6\";\n-\t\t\t\tregulator-min-microvolt = <1100000>;\n-\t\t\t\tregulator-max-microvolt = <1100000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 1V8_NVCC_SNVS */\n-\t\t\tldo1_reg: LDO1 {\n-\t\t\t\tregulator-name = \"ldo1\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 0V8_VDD_SNVS */\n-\t\t\tldo2_reg: LDO2 {\n-\t\t\t\tregulator-name = \"ldo2\";\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-max-microvolt = <800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 1V8_VDDA */\n-\t\t\tldo3_reg: LDO3 {\n-\t\t\t\tregulator-name = \"ldo3\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 0V9_VDD_PHY */\n-\t\t\tldo4_reg: LDO4 {\n-\t\t\t\tregulator-name = \"ldo4\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <900000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\t/* 1V2_VDD_PHY */\n-\t\t\tldo6_reg: LDO6 {\n-\t\t\t\tregulator-name = \"ldo6\";\n-\t\t\t\tregulator-min-microvolt = <1200000>;\n-\t\t\t\tregulator-max-microvolt = <1200000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&i2c2 {\n-\t/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c2>;\n-\tpinctrl-1 = <&pinctrl_i2c2_gpio>;\n-\tscl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\tusb-hub@2c {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usb_hub>;\n-\t\tcompatible = \"microchip,usb2514bi\";\n-\t\treg = <0x2c>;\n-\t\tindividual-port-switching;\n-\t\treset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;\n-\t\tself-powered;\n-\t};\n-\n-\teeprom: eeprom@50 {\n-\t\tcompatible = \"atmel,24c32\";\n-\t\treg = <0x50>;\n-\t\tpagesize = <32>;\n-\t};\n-\n-\trtc: rtc@68 {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_rtc>;\n-\t\tcompatible = \"st,m41t62\";\n-\t\treg = <0x68>;\n-\t\tinterrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;\n-\t};\n-\n-\tpcieclk: clk@6a {\n-\t\tcompatible = \"renesas,9fgv0241\";\n-\t\treg = <0x6a>;\n-\t\tclocks = <&clk_xtal25>;\n-\t\t#clock-cells = <1>;\n-\t};\n-};\n-\n-&i2c3 {\t/* Display connector I2C */\n-\t/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */\n-\tclock-frequency = <320000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c3>;\n-\tpinctrl-1 = <&pinctrl_i2c3_gpio>;\n-\tscl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-};\n-\n-&i2c4 {\t/* Feature connector I2C */\n-\t/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */\n-\tclock-frequency = <320000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c4>;\n-\tpinctrl-1 = <&pinctrl_i2c4_gpio>;\n-\tscl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,\n-\t\t <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,\n-\t\t <&pinctrl_panel_expansion>;\n-\n-\tpinctrl_ecspi1: ecspi1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK\t\t0x44\n-\t\t\tMX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI\t\t0x44\n-\t\t\tMX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO\t\t0x44\n-\t\t\tMX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi2: ecspi2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK\t\t0x44\n-\t\t\tMX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI\t\t0x44\n-\t\t\tMX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO\t\t0x44\n-\t\t\tMX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi3: ecspi3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK\t\t0x44\n-\t\t\tMX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI\t\t0x44\n-\t\t\tMX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO\t\t0x44\n-\t\t\tMX8MM_IOMUXC_UART2_TXD_GPIO5_IO25\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec1: fec1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_ENET_MDC_ENET1_MDC\t\t\t0x3\n-\t\t\tMX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO\t\t0x3\n-\t\t\tMX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t\t0x1f\n-\t\t\tMX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\t/* ENET_RST# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1\t\t0x6\n-\t\t\t/* ENET_WOL# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11\t\t0x40000090\n-\t\t\t/* ENET_INT# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_feature: hog-feature-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO4_IO27 */\n-\t\t\tMX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27\t\t0x40000006\n-\t\t\t/* GPIO5_IO03 */\n-\t\t\tMX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3\t\t\t0x40000006\n-\t\t\t/* GPIO5_IO04 */\n-\t\t\tMX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4\t\t\t0x40000006\n-\n-\t\t\t/* CAN_INT# */\n-\t\t\tMX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25\t\t0x40000090\n-\t\t\t/* CAN_RST# */\n-\t\t\tMX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26\t\t0x26\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_panel: hog-panel-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GRAPHICS_GPIO0_1V8 */\n-\t\t\tMX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7\t\t0x26\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_misc: hog-misc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* PG_V_IN_VAR# */\n-\t\t\tMX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1\t\t0x40000000\n-\t\t\t/* CSI_PD_1V8 */\n-\t\t\tMX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8\t\t0x0\n-\t\t\t/* CSI_RESET_1V8# */\n-\t\t\tMX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9\t\t0x0\n-\n-\t\t\t/* DIS_USB_DN1 */\n-\t\t\tMX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1\t\t\t0x0\n-\t\t\t/* DIS_USB_DN2 */\n-\t\t\tMX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28\t\t0x0\n-\n-\t\t\t/* EEPROM_WP_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5\t\t0x100\n-\t\t\t/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6\t\t0x0\n-\t\t\t/* GRAPHICS_PRSNT_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7\t\t0x40000000\n-\n-\t\t\t/* CLK_CCM_CLKO1_3V3 */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1\t0x10\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_sbc: hog-sbc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* MEMCFG[0..2] straps */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8\t\t0x40000140\n-\t\t\tMX8MM_IOMUXC_SD1_CMD_GPIO2_IO1\t\t\t0x40000140\n-\t\t\tMX8MM_IOMUXC_SD1_CLK_GPIO2_IO0\t\t\t0x40000140\n-\n-\t\t\t/* BOOT_CFG[0..15] straps */\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19\t\t0x40000000\n-\n-\t\t\t/* Not connected pins */\n-\t\t\tMX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20\t\t0x0\n-\t\t\tMX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10\t\t0x0\n-\t\t\tMX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11\t\t0x0\n-\t\t\tMX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0\t\t0x0\n-\t\t\tMX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1\t\t\t0x0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C1_SCL_I2C1_SCL\t\t\t0x40000084\n-\t\t\tMX8MM_IOMUXC_I2C1_SDA_I2C1_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1_gpio: i2c1-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14\t\t0x84\n-\t\t\tMX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c2: i2c2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C2_SCL_I2C2_SCL\t\t\t0x40000084\n-\t\t\tMX8MM_IOMUXC_I2C2_SDA_I2C2_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c2_gpio: i2c2-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16\t\t0x84\n-\t\t\tMX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3: i2c3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C3_SCL_I2C3_SCL\t\t\t0x40000084\n-\t\t\tMX8MM_IOMUXC_I2C3_SDA_I2C3_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3_gpio: i2c3-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18\t\t0x84\n-\t\t\tMX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4: i2c4-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C4_SCL_I2C4_SCL\t\t\t0x40000084\n-\t\t\tMX8MM_IOMUXC_I2C4_SDA_I2C4_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c4_gpio: i2c4-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20\t\t0x84\n-\t\t\tMX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_backlight: panel-backlight-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* BL_ENABLE_1V8 */\n-\t\t\tMX8MM_IOMUXC_NAND_ALE_GPIO3_IO0\t\t\t0x104\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_expansion: panel-expansion-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* DSI_RESET_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2\t\t0x2\n-\t\t\t/* DSI_IRQ_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_vcc_reg: panel-vcc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* TFT_ENABLE_1V8 */\n-\t\t\tMX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6\t\t0x104\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_pwm: panel-pwm-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* BL_PWM_3V3 */\n-\t\t\tMX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT\t\t0x12\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pcie0: pcie-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* M2-B_RESET_1V8# */\n-\t\t\tMX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20\t\t0x102\n-\t\t\t/* M2-B_PCIE_RST# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5\t\t0x2\n-\t\t\t/* M2-B_FULL_CARD_PWROFF_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4\t\t0x102\n-\t\t\t/* M2-B_W_DISABLE1_WWAN_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10\t\t0x102\n-\t\t\t/* M2-B_W_DISABLE2_GPS_1V8# */\n-\t\t\tMX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11\t\t0x102\n-\t\t\t/* CLK_M2_32K768 */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K\t0x14\n-\t\t\t/* M2-B_WAKE_WWAN_1V8# */\n-\t\t\tMX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19\t\t0x40000140\n-\t\t\t/* M2-B_PCIE_WAKE# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6\t\t0x40000140\n-\t\t\t/* M2-B_PCIE_CLKREQ# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9\t\t0x40000140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pmic: pmic-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_rtc: rtc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* RTC_IRQ# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai5: sai5-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK\t\t0x100\n-\t\t\tMX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0\t\t0x0\n-\t\t\tMX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC\t\t0x100\n-\t\t\tMX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK\t\t0x100\n-\t\t\tMX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0\t\t0x100\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX\t\t0x90\n-\t\t\tMX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B\t\t0x90\n-\t\t\tMX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX\t\t0x50\n-\t\t\tMX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B\t\t0x50\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B\t\t0x50\n-\t\t\tMX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B\t\t0x90\n-\t\t\tMX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX\t\t0x50\n-\t\t\tMX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX\t\t0x90\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart3: uart3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX\t\t0x40\n-\t\t\tMX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart4: uart4-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX\t\t0x40\n-\t\t\tMX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usb_hub: usb-hub-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* USBHUB_RESET# */\n-\t\t\tMX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2\t\t0x4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usb_otg1: usb-otg1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10\t\t0x40000000\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR\t\t0x4\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19\t\t0x4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x190\n-\t\t\tMX8MM_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_SD2_WP_USDHC2_WP\t\t\t0x400000d6\n-\t\t\tMX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B\t\t0x0d6\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x194\n-\t\t\tMX8MM_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_SD2_WP_USDHC2_WP\t\t\t0x400000d6\n-\t\t\tMX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B\t\t0x0d6\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_SD2_CLK_USDHC2_CLK\t\t\t0x196\n-\t\t\tMX8MM_IOMUXC_SD2_CMD_USDHC2_CMD\t\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_SD2_WP_USDHC2_WP\t\t\t0x400000d6\n-\t\t\tMX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B\t\t0x0d6\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: usdhc3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK\t\t0x190\n-\t\t\tMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7\t\t0x1d0\n-\t\t\tMX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE\t\t0x190\n-\t\t\tMX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK\t\t0x194\n-\t\t\tMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7\t\t0x1d4\n-\t\t\tMX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE\t\t0x194\n-\t\t\tMX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK\t\t0x196\n-\t\t\tMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7\t\t0x1d6\n-\t\t\tMX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE\t\t0x196\n-\t\t\tMX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_watchdog_gpio: watchdog-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* WDOG_B# */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2\t\t0x26\n-\t\t\t/* WDOG_EN -- ungate WDT RESET# signal propagation */\n-\t\t\tMX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9\t\t0x6\n-\t\t\t/* WDOG_KICK# / WDI */\n-\t\t\tMX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8\t\t0x26\n-\t\t>;\n-\t};\n-};\n-\n-&pcie_phy {\n-\tfsl,clkreq-unsupported;\t/* CLKREQ_B is not connected to suitable input */\n-\tfsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;\n-\tfsl,tx-deemph-gen1 = <0x2d>;\n-\tfsl,tx-deemph-gen2 = <0xf>;\n-\tclocks = <&pcieclk 0>;\n-\tstatus = \"okay\";\n-};\n-\n-&pcie0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_pcie0>;\n-\treset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;\n-\tclocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,\n-\t\t <&pcieclk 0>;\n-\tclock-names = \"pcie\", \"pcie_aux\", \"pcie_bus\";\n-\tassigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,\n-\t\t\t <&clk IMX8MM_CLK_PCIE1_CTRL>;\n-\tassigned-clock-rates = <10000000>, <250000000>;\n-\tassigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,\n-\t\t\t\t <&clk IMX8MM_SYS_PLL2_250M>;\n-\tstatus = \"okay\";\n-};\n-\n-&pwm1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_panel_pwm>;\n-\t/* Disabled by default, unless display board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-&sai5 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_sai5>;\n-\tfsl,sai-mclk-direction-output;\n-\t/* Input into codec PLL */\n-\tassigned-clocks = <&clk IMX8MM_CLK_SAI5>;\n-\tassigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;\n-\tassigned-clock-rates = <22579200>;\n-\t/* Disabled by default, unless display board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-&uart1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tuart-has-rtscts;\n-\tstatus = \"disabled\";\n-};\n-\n-&uart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tstatus = \"disabled\";\n-};\n-\n-&uart3 {\t/* A53 Debug */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart3>;\n-\tstatus = \"okay\";\n-};\n-\n-&uart4 {\t/* M4 Debug */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart4>;\n-\t/* UART4 is reserved for CM and RDC blocks CA access to UART4. */\n-\tstatus = \"disabled\";\n-};\n-\n-&usbotg1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usb_otg1>;\n-\tdr_mode = \"otg\";\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg2 {\n-\tdisable-over-current;\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc2 {\t/* MicroSD */\n-\tassigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>;\n-\tbus-width = <4>;\n-\tvmmc-supply = <®_usdhc2_vcc>;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc3 {\t/* eMMC */\n-\tassigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;\n-\tassigned-clock-rates = <400000000>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc3>;\n-\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tvmmc-supply = <&buck4_reg>;\n-\tvqmmc-supply = <&buck5_reg>;\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex fbabd17288f..db138a8da34 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -92,6 +92,7 @@ config TARGET_IMX8MM_DATA_MODUL_EDM_SBC\n \tselect IMX8MM\n \tselect IMX8M_LPDDR4\n \tselect SUPPORT_SPL\n+\timply OF_UPSTREAM\n \n config TARGET_IMX8MM_EVK\n \tbool \"imx8mm LPDDR4 EVK board\"\ndiff --git a/board/data_modul/imx8mm_edm_sbc/MAINTAINERS b/board/data_modul/imx8mm_edm_sbc/MAINTAINERS\nindex 36af19b78f9..46f591f4f03 100644\n--- a/board/data_modul/imx8mm_edm_sbc/MAINTAINERS\n+++ b/board/data_modul/imx8mm_edm_sbc/MAINTAINERS\n@@ -1,7 +1,6 @@\n Data Modul eDM SBC i.MX8M Mini\n M:\tMarek Vasut <marex@denx.de>\n S:\tMaintained\n-F:\tarch/arm/dts/imx8mm-data-modul-edm-sbc.dts\n F:\tarch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi\n F:\tboard/data_modul/imx8mm_edm_sbc/\n F:\tconfigs/imx8mm_data_modul_edm_sbc_defconfig\ndiff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig\nindex 47f0d3cc050..70dad87f3ff 100644\n--- a/configs/imx8mm_data_modul_edm_sbc_defconfig\n+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig\n@@ -6,7 +6,7 @@ CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y\n CONFIG_CI_UDC=y\n CONFIG_CLK_IMX8MM=y\n CONFIG_CMD_PCI=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mm-data-modul-edm-sbc\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mm-data-modul-edm-sbc\"\n CONFIG_DEFAULT_FDT_FILE=\"imx8mm-data-modul-edm-sbc.dtb\"\n CONFIG_DM_PMIC_BD71837=y\n CONFIG_DM_REGULATOR_BD71837=y\n", "prefixes": [ "09/13" ] }