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GET /api/1.1/patches/2228186/?format=api
{ "id": 2228186, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228186/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-12-07527be92e5d@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260425-imx8m-of-upstream-v1-12-07527be92e5d@nxp.com>", "date": "2026-04-25T00:37:04", "name": "[12/13] imx8mp: data-modul-edm-sbc: Switch to OF_UPSTREAM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e085b29f33a09d52bf139ecdbc383baf8f5d34b0", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/1.1/people/80723/?format=api", "name": "Peng Fan (OSS)", "email": "peng.fan@oss.nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260425-imx8m-of-upstream-v1-12-07527be92e5d@nxp.com/mbox/", "series": [ { "id": 501451, "url": "http://patchwork.ozlabs.org/api/1.1/series/501451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501451", "date": "2026-04-25T00:37:04", "name": "iMX8M: Covert to OF_UPSTREAM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501451/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228186/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228186/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=xAC4qgWw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260425-imx8m-of-upstream-v1-12-07527be92e5d@nxp.com>", "References": "<20260425-imx8m-of-upstream-v1-0-07527be92e5d@nxp.com>", "In-Reply-To": "<20260425-imx8m-of-upstream-v1-0-07527be92e5d@nxp.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n kernel@puri.sm, u-boot@dh-electronics.com", "Cc": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Tom Rini <trini@konsulko.com>, \"Lukas F. Hartmann\" <lukas@mntre.com>,\n Patrick Wildt <patrick@blueri.se>, Ye Li <ye.li@nxp.com>,\n Frieder Schrempf <frieder.schrempf@kontron.de>,\n Benjamin Hahn <B.Hahn@phytec.de>, Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n Angus Ainslie <angus@akkea.ca>, Heiko Thiery <heiko.thiery@gmail.com>,\n Olaf Mandel <o.mandel@menlosystems.com>,\n Jagan Teki <jagan@amarulasolutions.com>,\n Matteo Lisi <matteo.lisi@engicam.com>,\n Manoj Sai <abbaraju.manojsai@amarulasolutions.com>,\n Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n Parth Pancholi <parth.pancholi@toradex.com>, Peng Fan <peng.fan@nxp.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "SI2PR01CA0020.apcprd01.prod.exchangelabs.com\n (2603:1096:4:192::6) To PAXPR04MB8459.eurprd04.prod.outlook.com\n (2603:10a6:102:1da::15)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "\n PAXPR04MB8459:EE_|AM8PR04MB7876:EE_|DU4PR04MB10670:EE_", "X-MS-Office365-Filtering-Correlation-Id": "135837a3-f096-4a65-59b3-08dea2583bb8", "X-MS-Exchange-SharedMailbox-RoutingAgent-Processed": "True", "X-LD-Processed": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|7416014|376014|52116014|1800799024|19092799006|366016|56012099003|18002099003|22082099003|38350700014;", "X-Microsoft-Antispam-Message-Info": "\n Gg783Uvbk6SI40+LiUdfCJoIw3a9cHamhHLUUBDyS5WPG87wBSSPwBH6MC1a66nfJSbWWtmzV+J0j7pExx3UhPDzahYLNIulizJRcpJP/m4r+4Zy4WQxATm4yKIeoXQqZs190tx2BX6Lot3wLH4vcbHBJy7RXQm9lq+qOL/VtglnKuDJ6lnbj8mh/P4Zt1RuDlAqR9UIwqLa0S+X56jYZ0Dlh+c1fVs2Q2YuzYo0bnxf18ncNVUVr4hEmOCWNVoFYuBk1pUTjIlRCTdjIS7X6szDGjCKHNvOF2+cyQGXD4kSj34uBiPBQVPGFqJ0JAHr1O/F81VH0+6ZjJpayOe4jEJ4cBlryh2uVVwOsSiABREIccY5iCSe0EzbWZ0yCYy+3bA8y9vTnO9Qb3weojkbI7tdRdws6IcSknrU6M08XycnVQEyzRY8l+4JbEkxezXEPzACQWirs5pXeNgy54xlfjyFkWR4R19CLBFMXKOeymxPKfAEUTjvyUVhHNjwRTkz/YAydXd7DgkAkcp2wzcXsm57qDd5ZEBgtkwE53NnjOGoXR9xf8lXF6jN4lX6h7upJ4sg4t7N58QdN/+5CeHzb/7oub26/wjJWHn+LGs9JAup5NpcW4mRYbM9kKHx1ZWFEX9mRg5Bowy5toC5wEuNQXgI/8WVDa10yBbUp1SXOX1nE3Z3bqafcf9+Ce/zvCS/GShSzWmp2C93qEHek2R/yvcPYUcUOv5NXpp7sldqHAAgSwBlmvPAMxb4mLCaQdgTEQxDgXBiIK1IxuoAgXJvH2cINW0fYqlyI8iGEIPAB8s=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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So change is update eeprom alias to node eeprom902.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi | 2 +-\n arch/arm/dts/imx8mp-data-modul-edm-sbc.dts | 972 ---------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n board/data_modul/imx8mp_edm_sbc/MAINTAINERS | 1 -\n configs/imx8mp_data_modul_edm_sbc_defconfig | 2 +-\n 6 files changed, 3 insertions(+), 976 deletions(-)", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 434bcbfef32..d2ddf885c1a 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -875,7 +875,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \\\n dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mm-phg.dtb \\\n \timx8mq-cm.dtb \\\n-\timx8mp-data-modul-edm-sbc.dtb \\\n \timx8mp-dhcom-som-overlay-rev100.dtbo \\\n \timx8mp-dhcom-som-overlay-eth1xfast.dtbo \\\n \timx8mp-dhcom-som-overlay-eth2xfast.dtbo \\\ndiff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi\nindex 1e82e718b8f..a4d5ed1649f 100644\n--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi\n+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi\n@@ -8,7 +8,7 @@\n \n / {\n \taliases {\n-\t\teeprom0 = &eeprom;\n+\t\teeprom0 = &eeprom902;\n \t\tmmc0 = &usdhc3;\t/* eMMC */\n \t\tmmc1 = &usdhc2;\t/* MicroSD */\n \t\tspi0 = &ecspi1;\ndiff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts\ndeleted file mode 100644\nindex 6b40106e3bd..00000000000\n--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts\n+++ /dev/null\n@@ -1,972 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (C) 2022 Marek Vasut <marex@denx.de>\n- */\n-\n-/dts-v1/;\n-\n-#include <dt-bindings/net/qca-ar803x.h>\n-#include \"imx8mp.dtsi\"\n-\n-/ {\n-\tmodel = \"Data Modul i.MX8M Plus eDM SBC\";\n-\tcompatible = \"dmo,imx8mp-data-modul-edm-sbc\", \"fsl,imx8mp\";\n-\n-\taliases {\n-\t\trtc0 = &rtc;\n-\t\trtc1 = &snvs_rtc;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = &uart3;\n-\t};\n-\n-\tmemory@40000000 {\n-\t\tdevice_type = \"memory\";\n-\t\t/* There are 1/2/4 GiB options, adjusted by bootloader. */\n-\t\treg = <0x0 0x40000000 0 0x40000000>;\n-\t};\n-\n-\tbacklight: backlight {\n-\t\tcompatible = \"pwm-backlight\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_panel_backlight>;\n-\t\tbrightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;\n-\t\tdefault-brightness-level = <7>;\n-\t\tenable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;\n-\t\tpwms = <&pwm1 0 5000000 0>;\n-\t\t/* Disabled by default, unless display board plugged in. */\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tclk_xtal25: clk-xtal25 {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <25000000>;\n-\t};\n-\n-\tpanel: panel {\n-\t\tbacklight = <&backlight>;\n-\t\tpower-supply = <®_panel_vcc>;\n-\t\t/* Disabled by default, unless display board plugged in. */\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\treg_panel_vcc: regulator-panel-vcc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_panel_vcc_reg>;\n-\t\tregulator-name = \"PANEL_VCC\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tgpio = <&gpio3 6 0>;\n-\t\tenable-active-high;\n-\t\t/* Disabled by default, unless display board plugged in. */\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\treg_usdhc2_vmmc: regulator-usdhc2-vmmc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tenable-active-high;\n-\t\tgpio = <&gpio2 19 0>; /* SD2_RESET */\n-\t\toff-on-delay-us = <12000>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usdhc2_vmmc>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"VDD_3V3_SD\";\n-\t\tstartup-delay-us = <100>;\n-\t\tvin-supply = <&buck4>;\n-\t};\n-\n-\twatchdog {\n-\t\t/* TPS3813 */\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_watchdog_gpio>;\n-\t\tcompatible = \"linux,wdt-gpio\";\n-\t\talways-running;\n-\t\tgpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;\n-\t\thw_algo = \"level\";\n-\t\t/* Reset triggers in 2..3 seconds */\n-\t\thw_margin_ms = <1500>;\n-\t\t/* Disabled by default */\n-\t\tstatus = \"disabled\";\n-\t};\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <&buck2>;\n-};\n-\n-&ecspi1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi1>;\n-\tcs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;\n-\tstatus = \"okay\";\n-\n-\tflash@0 {\t/* W25Q128JVEI */\n-\t\tcompatible = \"jedec,spi-nor\";\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <100000000>;\t/* Up to 133 MHz */\n-\t\tspi-tx-bus-width = <1>;\n-\t\tspi-rx-bus-width = <1>;\n-\t};\n-};\n-\n-&ecspi2 {\t/* Feature connector SPI */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi2>;\n-\tcs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;\n-\t/* Disabled by default, unless feature board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-&ecspi3 {\t/* Display connector SPI */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi3>;\n-\tcs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;\n-\t/* Disabled by default, unless display board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-&eqos {\t/* First ethernet */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_eqos>;\n-\tphy-handle = <&phy_eqos>;\n-\tphy-mode = \"rgmii-id\";\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\tcompatible = \"snps,dwmac-mdio\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* Atheros AR8031 PHY */\n-\t\tphy_eqos: ethernet-phy@0 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <0>;\n-\t\t\t/*\n-\t\t\t * Dedicated ENET_WOL# signal is unused, the PHY\n-\t\t\t * can wake the SoC up via INT signal as well.\n-\t\t\t */\n-\t\t\tinterrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\treset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t\treset-deassert-us = <10000>;\n-\t\t\tqca,keep-pll-enabled;\n-\t\t\tvddio-supply = <&vddio_eqos>;\n-\n-\t\t\tvddio_eqos: vddio-regulator {\n-\t\t\t\tregulator-name = \"VDDIO_EQOS\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t};\n-\n-\t\t\tvddh_eqos: vddh-regulator {\n-\t\t\t\tregulator-name = \"VDDH_EQOS\";\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&fec {\t/* Second ethernet */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_fec>;\n-\tphy-handle = <&phy_fec>;\n-\tphy-mode = \"rgmii-id\";\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* Atheros AR8031 PHY */\n-\t\tphy_fec: ethernet-phy@0 {\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <0>;\n-\t\t\t/*\n-\t\t\t * Dedicated ENET_WOL# signal is unused, the PHY\n-\t\t\t * can wake the SoC up via INT signal as well.\n-\t\t\t */\n-\t\t\tinterrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\treset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t\treset-deassert-us = <10000>;\n-\t\t\tqca,keep-pll-enabled;\n-\t\t\tvddio-supply = <&vddio_fec>;\n-\n-\t\t\tvddio_fec: vddio-regulator {\n-\t\t\t\tregulator-name = \"VDDIO_FEC\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t};\n-\n-\t\t\tvddh_fec: vddh-regulator {\n-\t\t\t\tregulator-name = \"VDDH_FEC\";\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&flexcan1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_flexcan1>;\n-\tstatus = \"okay\";\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"\", \"USBHUB_RESET#\", \"WDOG_B#\", \"PMIC_INT#\",\n-\t\t\"\", \"M2_PCIE_RST#\", \"M2_PCIE_WAKE#\", \"GPIO5_IO03\",\n-\t\t\"GPIO5_IO04\", \"PDM_SEL\", \"ENET_WOL#\", \"ENET_INT#\",\n-\t\t\"\", \"\", \"\", \"ENET_RST#\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"ENET2_INT#\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"WDOG_KICK#\", \"ENET2_RST#\", \"CAN_INT#\", \"RTC_IRQ#\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"SD2_RESET#\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names =\n-\t\t\"BL_ENABLE_1V8\", \"PG_V_IN_VAR#\", \"\", \"\",\n-\t\t\"\", \"\", \"TFT_ENABLE_1V8\", \"GRAPHICS_GPIO0_1V8\",\n-\t\t\"CSI2_PD_1V8\", \"CSI2_RESET_1V8#\", \"\", \"\",\n-\t\t\"\", \"\", \"EEPROM_WP_1V8#\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"MEMCFG0\", \"PCIE_CLK_GEN_CLKPWRGD_PD_1V8#\",\n-\t\t\"\", \"M2_W_DISABLE1_1V8#\",\n-\t\t\"M2_W_DISABLE2_1V8#\", \"\", \"I2C5_SCL_3V3\", \"I2C5_SDA_3V3\",\n-\t\t\"\", \"\", \"\", \"\";\n-};\n-\n-&gpio4 {\n-\tgpio-line-names =\n-\t\t\"DSI_RESET_1V8#\", \"MEMCFG2\", \"\", \"MEMCFG1\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n-\t\t\"\", \"\", \"GRAPHICS_PRSNT_1V8#\", \"DSI_IRQ_1V8#\",\n-\t\t\"\", \"DIS_USB_DN1\", \"DIS_USB_DN2\", \"\",\n-\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names =\n-\t\t\"\", \"\", \"\", \"\", \"\", \"WDOG_EN\", \"\", \"\",\n-\t\t\"\", \"SPI1_CS#\", \"\", \"\",\n-\t\t\"\", \"SPI2_CS#\", \"I2C1_SCL_3V3\", \"I2C1_SDA_3V3\",\n-\t\t\"I2C2_SCL_3V3\", \"I2C2_SDA_3V3\", \"I2C3_SCL_3V3\", \"I2C3_SDA_3V3\",\n-\t\t\"\", \"\", \"\", \"\",\n-\t\t\"\", \"SPI3_CS#\", \"\", \"\", \"\", \"\", \"\", \"\";\n-};\n-\n-&i2c1 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n-\tscl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\tusb-hub@2c {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usb_hub>;\n-\t\tcompatible = \"microchip,usb2514bi\";\n-\t\treg = <0x2c>;\n-\t\tindividual-port-switching;\n-\t\treset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n-\t\tself-powered;\n-\t};\n-\n-\teeprom: eeprom@50 {\n-\t\tcompatible = \"atmel,24c32\";\n-\t\treg = <0x50>;\n-\t\tpagesize = <32>;\n-\t};\n-\n-\trtc: rtc@68 {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_rtc>;\n-\t\tcompatible = \"st,m41t62\";\n-\t\treg = <0x68>;\n-\t\tinterrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;\n-\t};\n-\n-\tpcieclk: clk@6a {\n-\t\tcompatible = \"renesas,9fgv0241\";\n-\t\treg = <0x6a>;\n-\t\tclocks = <&clk_xtal25>;\n-\t\t#clock-cells = <1>;\n-\t};\n-};\n-\n-&i2c2 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c2>;\n-\tpinctrl-1 = <&pinctrl_i2c2_gpio>;\n-\tscl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-};\n-\n-&i2c3 {\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c3>;\n-\tpinctrl-1 = <&pinctrl_i2c3_gpio>;\n-\tscl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\tpmic: pmic@25 {\n-\t\tcompatible = \"nxp,pca9450c\";\n-\t\treg = <0x25>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pmic>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <3 IRQ_TYPE_LEVEL_LOW>;\n-\n-\t\t/*\n-\t\t * i.MX 8M Plus Data Sheet for Consumer Products\n-\t\t * 3.1.4 Operating ranges\n-\t\t * MIMX8ML8CVNKZAB\n-\t\t */\n-\t\tregulators {\n-\t\t\tbuck1: BUCK1 {\t/* VDD_SOC (dual-phase with BUCK3) */\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck2: BUCK2 {\t/* VDD_ARM */\n-\t\t\t\tregulator-min-microvolt = <850000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck4: BUCK4 {\t/* VDD_3V3 */\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck5: BUCK5 {\t/* VDD_1V8 */\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tbuck6: BUCK6 {\t/* NVCC_DRAM_1V1 */\n-\t\t\t\tregulator-min-microvolt = <1100000>;\n-\t\t\t\tregulator-max-microvolt = <1100000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo1: LDO1 {\t/* NVCC_SNVS_1V8 */\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo3: LDO3 {\t/* VDDA_1V8 */\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t};\n-\n-\t\t\tldo4: LDO4 {\t/* PMIC_LDO4 */\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t};\n-\n-\t\t\tldo5: LDO5 {\t/* NVCC_SD2 */\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&i2c5 {\t/* HDMI EDID bus */\n-\tclock-frequency = <100000>;\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_i2c5>;\n-\tpinctrl-1 = <&pinctrl_i2c5_gpio>;\n-\tscl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,\n-\t\t <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,\n-\t\t <&pinctrl_panel_expansion>;\n-\n-\tpinctrl_ecspi1: ecspi1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi2: ecspi2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO\t\t0x44\n-\t\t\tMX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ecspi3: ecspi3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK\t\t0x44\n-\t\t\tMX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI\t\t0x44\n-\t\t\tMX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO\t\t0x44\n-\t\t\tMX8MP_IOMUXC_UART2_TXD__GPIO5_IO25\t\t0x40\n-\t\t>;\n-\t};\n-\n-\tpinctrl_eqos: eqos-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC\t\t0x3\n-\t\t\tMX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO\t\t0x3\n-\t\t\tMX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3\t0x1f\n-\t\t\tMX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2\t0x91\n-\t\t\tMX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3\t0x91\n-\t\t\t/* ENET_RST# */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15\t\t0x6\n-\t\t\t/* ENET_INT# */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec: fec-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC\t\t0x3\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO\t\t0x3\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC\t\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC\t\t0x1f\n-\t\t\t/* ENET2_RST# */\n-\t\t\tMX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09\t\t0x6\n-\t\t\t/* ENET2_INT# */\n-\t\t\tMX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_flexcan1: flexcan1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SPDIF_RX__CAN1_RX\t\t\t0x154\n-\t\t\tMX8MP_IOMUXC_SPDIF_TX__CAN1_TX\t\t\t0x154\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_feature: hog-feature-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GPIO5_IO03 */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07\t\t0x40000006\n-\t\t\t/* GPIO5_IO04 */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08\t\t0x40000006\n-\n-\t\t\t/* CAN_INT# */\n-\t\t\tMX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_panel: hog-panel-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* GRAPHICS_GPIO0_1V8 */\n-\t\t\tMX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07\t\t0x26\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_misc: hog-misc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* ENET_WOL# -- shared by both PHYs */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10\t\t0x40000090\n-\n-\t\t\t/* PG_V_IN_VAR# */\n-\t\t\tMX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01\t\t0x40000000\n-\t\t\t/* CSI2_PD_1V8 */\n-\t\t\tMX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08\t\t0x0\n-\t\t\t/* CSI2_RESET_1V8# */\n-\t\t\tMX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09\t\t0x0\n-\n-\t\t\t/* DIS_USB_DN1 */\n-\t\t\tMX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21\t\t0x0\n-\t\t\t/* DIS_USB_DN2 */\n-\t\t\tMX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22\t\t0x0\n-\n-\t\t\t/* EEPROM_WP_1V8# */\n-\t\t\tMX8MP_IOMUXC_NAND_DQS__GPIO3_IO14\t\t0x100\n-\t\t\t/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21\t\t0x0\n-\t\t\t/* GRAPHICS_PRSNT_1V8# */\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18\t\t0x40000000\n-\n-\t\t\t/* CLK_CCM_CLKO1_3V3 */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1\t\t0x10\n-\t\t>;\n-\t};\n-\n-\tpinctrl_hog_sbc: hog-sbc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* MEMCFG[0..2] straps */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20\t\t0x40000140\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03\t\t0x40000140\n-\t\t\tMX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01\t\t0x40000140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C1_SCL__I2C1_SCL\t\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_I2C1_SDA__I2C1_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1_gpio: i2c1-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14\t\t0x84\n-\t\t\tMX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c2: i2c2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C2_SCL__I2C2_SCL\t\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_I2C2_SDA__I2C2_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c2_gpio: i2c2-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16\t\t0x84\n-\t\t\tMX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3: i2c3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C3_SCL__I2C3_SCL\t\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_I2C3_SDA__I2C3_SDA\t\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3_gpio: i2c3-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18\t\t0x84\n-\t\t\tMX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c5: i2c5-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL\t\t0x40000084\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA\t\t0x40000084\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c5_gpio: i2c5-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26\t\t0x84\n-\t\t\tMX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27\t\t0x84\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_backlight: panel-backlight-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* BL_ENABLE_1V8 */\n-\t\t\tMX8MP_IOMUXC_NAND_ALE__GPIO3_IO00\t\t0x104\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_expansion: panel-expansion-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* DSI_RESET_1V8# */\n-\t\t\tMX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00\t\t0x2\n-\t\t\t/* DSI_IRQ_1V8# */\n-\t\t\tMX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_pwm: panel-pwm-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* BL_PWM_3V3 */\n-\t\t\tMX8MP_IOMUXC_I2C4_SDA__PWM1_OUT\t\t\t0x12\n-\t\t>;\n-\t};\n-\n-\tpinctrl_panel_vcc_reg: panel-vcc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* TFT_ENABLE_1V8 */\n-\t\t\tMX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06\t\t0x104\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pcie0: pcie-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* M2_PCIE_RST# */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05\t\t0x2\n-\t\t\t/* M2_W_DISABLE1_1V8# */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23\t\t0x2\n-\t\t\t/* M2_W_DISABLE2_1V8# */\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24\t\t0x2\n-\t\t\t/* CLK_M2_32K768 */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1\t\t0x14\n-\t\t\t/* M2_PCIE_WAKE# */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06\t\t0x40000140\n-\t\t\t/* M2_PCIE_CLKREQ# */\n-\t\t\tMX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B\t\t0x61\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pdm: pdm-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* PDM_SEL */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09\t\t0x0\n-\t\t\tMX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK\t\t0x0\n-\t\t\tMX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00\t0x0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pmic: pmic-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* PMIC_nINT */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_rtc: rtc-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* RTC_IRQ# */\n-\t\t\tMX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11\t\t0x40000090\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai1: sai1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00\t0xd6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai2: sai2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK\t0xd6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai3: sai3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK\t0xd6\n-\t\t\tMX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00\t0xd6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS\t\t0x49\n-\t\t\tMX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart3: uart3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart4: uart4-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX\t\t0x49\n-\t\t\tMX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX\t\t0x49\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CLK__USDHC2_CLK\t\t0x190\n-\t\t\tMX8MP_IOMUXC_SD2_CMD__USDHC2_CMD\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CLK__USDHC2_CLK\t\t0x194\n-\t\t\tMX8MP_IOMUXC_SD2_CMD__USDHC2_CMD\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CLK__USDHC2_CLK\t\t0x196\n-\t\t\tMX8MP_IOMUXC_SD2_CMD__USDHC2_CMD\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT\t\t0xc1\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19\t\t0x20\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: usdhc2-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12\t\t0x40000080\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: usdhc3-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK\t\t0x190\n-\t\t\tMX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7\t\t0x1d0\n-\t\t\tMX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE\t\t0x190\n-\t\t\tMX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK\t\t0x194\n-\t\t\tMX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7\t\t0x1d4\n-\t\t\tMX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE\t\t0x194\n-\t\t\tMX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK\t\t0x196\n-\t\t\tMX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7\t\t0x1d6\n-\t\t\tMX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE\t\t0x196\n-\t\t\tMX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usb_hub: usb-hub-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* USBHUB_RESET# */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01\t\t0x4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usb1: usb1-grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR\t\t0x6\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC\t\t0x80\n-\t\t>;\n-\t};\n-\n-\tpinctrl_watchdog_gpio: watchdog-gpio-grp {\n-\t\tfsl,pins = <\n-\t\t\t/* WDOG_B# */\n-\t\t\tMX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B\t\t0x26\n-\t\t\t/* WDOG_EN -- ungate WDT RESET# signal propagation */\n-\t\t\tMX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05\t\t0x6\n-\t\t\t/* WDOG_KICK# / WDI */\n-\t\t\tMX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08\t\t0x26\n-\t\t>;\n-\t};\n-};\n-\n-&pwm1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_panel_pwm>;\n-\t/* Disabled by default, unless display board plugged in. */\n-\tstatus = \"disabled\";\n-};\n-\n-/* SD slot */\n-&usdhc2 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tcd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n-\tvmmc-supply = <®_usdhc2_vmmc>;\n-\tbus-width = <4>;\n-\tstatus = \"okay\";\n-};\n-\n-/* eMMC */\n-&usdhc3 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc3>;\n-\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n-\tvmmc-supply = <&buck4>;\n-\tvqmmc-supply = <&buck5>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\n-\n-&uart1 {\t/* RS485 */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tuart-has-rtscts;\n-\tstatus = \"disabled\";\t/* Optional */\n-};\n-\n-&uart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tuart-has-rtscts;\n-\tstatus = \"okay\";\n-};\n-\n-&uart3 {\t/* A53 Debug */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart3>;\n-\tstatus = \"okay\";\n-};\n-\n-&uart4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart4>;\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_0 {\n-\tfsl,over-current-active-low;\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_0 {\t/* Lower plug direct */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usb1>;\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_dwc3_1 {\t/* Upper plug via HUB */\n-\tdr_mode = \"host\";\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex 00b5963b30e..d56fc7bf7f1 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -237,6 +237,7 @@ config TARGET_IMX8MP_DATA_MODUL_EDM_SBC\n \tselect IMX8MP\n \tselect IMX8M_LPDDR4\n \tselect SUPPORT_SPL\n+\timply OF_UPSTREAM\n \n config TARGET_IMX8MP_BEACON\n \tbool \"imx8mm Beacon Embedded devkit\"\ndiff --git a/board/data_modul/imx8mp_edm_sbc/MAINTAINERS b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS\nindex 8a49c8a67d5..2b43b46b207 100644\n--- a/board/data_modul/imx8mp_edm_sbc/MAINTAINERS\n+++ b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS\n@@ -1,7 +1,6 @@\n Data Modul eDM SBC i.MX8M Plus\n M:\tMarek Vasut <marex@denx.de>\n S:\tMaintained\n-F:\tarch/arm/dts/imx8mp-data-modul-edm-sbc.dts\n F:\tarch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi\n F:\tboard/data_modul/imx8mp_edm_sbc/\n F:\tconfigs/imx8mp_data_modul_edm_sbc_defconfig\ndiff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig\nindex a30aaa57109..129bed9c2ff 100644\n--- a/configs/imx8mp_data_modul_edm_sbc_defconfig\n+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig\n@@ -4,7 +4,7 @@ CONFIG_ARM=y\n CONFIG_ARCH_IMX8M=y\n CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y\n CONFIG_CLK_IMX8MP=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mp-data-modul-edm-sbc\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mp-data-modul-edm-sbc\"\n CONFIG_DEFAULT_FDT_FILE=\"imx8mp-data-modul-edm-sbc.dtb\"\n CONFIG_DM_PMIC_PCA9450=y\n CONFIG_DM_REGULATOR_PCA9450=y\n", "prefixes": [ "12/13" ] }