Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2228163/?format=api
{ "id": 2228163, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228163/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/73ee67db-86a3-4329-85e7-a7d5945687dc@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<73ee67db-86a3-4329-85e7-a7d5945687dc@oss.qualcomm.com>", "date": "2026-04-25T15:01:35", "name": "[to-be-committed,RISC-V,PR,target/123904] Improve bit masking of shifted values", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a54c657579018203576801b6abcd5ae270f559ef", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/73ee67db-86a3-4329-85e7-a7d5945687dc@oss.qualcomm.com/mbox/", "series": [ { "id": 501445, "url": "http://patchwork.ozlabs.org/api/1.1/series/501445/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501445", "date": "2026-04-25T15:01:35", "name": "[to-be-committed,RISC-V,PR,target/123904] Improve bit masking of shifted values", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501445/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228163/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228163/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=B+A0HtgO;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=SdJy5o1M;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=B+A0HtgO;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=SdJy5o1M", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "sourceware.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=205.220.180.131" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2tN65PBwz1yHS\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 26 Apr 2026 01:02:12 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id CECB04BB58A1\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 25 Apr 2026 15:02:10 +0000 (GMT)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n by sourceware.org (Postfix) with ESMTPS id C1AE34BB3BBF\n for <gcc-patches@gcc.gnu.org>; Sat, 25 Apr 2026 15:01:41 +0000 (GMT)", "from pps.filterd (m0279869.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63P3SFM12954893\n for <gcc-patches@gcc.gnu.org>; Sat, 25 Apr 2026 15:01:41 GMT", "from mail-dy1-f197.google.com (mail-dy1-f197.google.com\n [74.125.82.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4drnqrh59d-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <gcc-patches@gcc.gnu.org>; Sat, 25 Apr 2026 15:01:40 +0000 (GMT)", "by mail-dy1-f197.google.com with SMTP id\n 5a478bee46e88-2c16233ee11so12204795eec.1\n for <gcc-patches@gcc.gnu.org>; Sat, 25 Apr 2026 08:01:40 -0700 (PDT)", "from [172.31.0.17] ([136.38.201.137])\n by smtp.gmail.com with ESMTPSA id\n 5a478bee46e88-2e53a4a8018sm46428330eec.8.2026.04.25.08.01.36\n for <gcc-patches@gcc.gnu.org>\n (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128);\n Sat, 25 Apr 2026 08:01:37 -0700 (PDT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org CECB04BB58A1", "OpenDKIM Filter v2.11.0 sourceware.org C1AE34BB3BBF" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org C1AE34BB3BBF", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org C1AE34BB3BBF", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777129301; cv=none;\n b=ON4oCL1A9trO1+SinySxZgCObnSOfLQxjtaE3Iy6ufngk7NCCwvRaYf/FuuAbDIAAETtmM+lXZ7vWkV4ljmzljzHIoCwvf5S49GL77hdklkMrwJUTKVxizHPc7u6E4biks+sAlOHUWknoIxga9QFJ4p+d3m2lgkriULOMFiF8yQ=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777129301; c=relaxed/simple;\n bh=Nj6fP424hqgpSjq++Cmi5PSqFQTfPuoJhLoe149ls6M=;\n h=DKIM-Signature:DKIM-Signature:Message-ID:Date:MIME-Version:From:\n To:Subject;\n b=goRicAwxDliMifUDH2QBnXOY7Fqnb8QEgxVSavE3SCH0em5RZ/xpYMGgcEzkHSmgBDmPStp+tJmIRkLSxk7mtDmQgOIiACvaPEY7RJUU0XyWVGp8cSJu/wt57TxOl8phoLx92zPlqau4KaT6lF8TRDCOJ6fCD/4MtRVv8DCRDbk=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n content-type:date:from:message-id:mime-version:subject:to; s=\n qcppdkim1; bh=4b3ayCOlGyguUw+iol/DAfMmm60IOj+mGG0y4B3xDnM=; b=B+\n A0HtgOiT2LCeNzvn83ynkMw+lYx+PL+k2QeqVZ44NsVeawL5CMrYLvReo5j6rGym\n Gb8qKhtgLLWvZggJ/TUdBQ2dPFRdaCUq/UjRsjFoXdUiVxPOitcuSXNZPWc6sMB5\n NysFzEAuAUVVf3etHSV+qj31QdPOSm2Xq5mPlA7GCU1GSb9nMWb1Tmf5JaVLtfIn\n qyKAfsfLhZGy5HQAxeQb/6cZuiQu1LzldiXrbD9Fu9zfigtSezoqDU8vQhv9RlMk\n KeCrVMj7CbMdhcgSk+3fkeFR8ONlppM7oF/UVQQD4wuKzsnMuEFdD3pR0FAsQm/c\n qO+CDsQaRDH6VzfRCR6w==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1777129299; x=1777734099; darn=gcc.gnu.org;\n h=subject:to:from:content-language:user-agent:mime-version:date\n :message-id:from:to:cc:subject:date:message-id:reply-to;\n bh=4b3ayCOlGyguUw+iol/DAfMmm60IOj+mGG0y4B3xDnM=;\n b=SdJy5o1Mi/F8Jks6VfWeNKJMixPSGCh9KuZuBRAC8L5sa2kTaKqbf79+q39pek/pjf\n RUgmx6cvLqfMoMBYc30fn9MPjTXJLKzH93OyL72nXQYvnr4vlPCgVQAUsOa6En36/1eP\n asnSLMCClPUU0wuY/+uufZfg8cVr5TOxlkf4iwzAIOBgcxdi8suAlD3qjrAFXygDMK82\n dbbnv1vKdyjxgXAIa2c1oEB5cDBKHg54StANrrt94nCUPJTRBVwH03gh/S95sf3NTriM\n 1O6lV/BP3P1Z/JDFIyMnFdk92EHUEmjCc1jSjXHQoxPjoY7SBjAPA0ngKKIVmJcMpWR4\n AEcg==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777129299; x=1777734099;\n h=subject:to:from:content-language:user-agent:mime-version:date\n :message-id:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=4b3ayCOlGyguUw+iol/DAfMmm60IOj+mGG0y4B3xDnM=;\n b=qeTc+igD3FNot04Ze3/IrcSmnzniXq2vuPs87AJeEYQWOn/rr83CYqUIHDZtYVv8DL\n Vmwq6S2OS4HnO3oiiGI3z6fd3x96B/TqOzrhIe3OB18i9nNB+wBJFTdcb539M8s6Zab/\n rUzfuvsXFM+uSEqRbLA0ORhSnWh1C0ru6XZsRxfq011PViOXNCQfPn3YhLuqayml4jAV\n n9ufTNF3ZauZo2P+3T0vXflaaKyXGDm4g52iPNZV50GttWaUmN+wMa/xo+HDu7K7meVY\n 9YkvV4/ZsNzGvhMx6OCyoFkF0bfsuQZL+SMwsylXCUZGd2wDI1du6Rq6IHDy5E+DHOnS\n KNpw==", "X-Gm-Message-State": "AOJu0Yzp6rp/DFLJS7cwtmuAy2KHBm/aUOpvpYJaXg+YhuGG0KnwU/SB\n gI2UpO7SfYOffMI4TBDR2B7yH0UEBQO6JYMtugdxwcBK9ImKl8SH64HB3HuNBRkhmLO6Twj0Noo\n s507tLlS5XFiKJKwl40angPgNN4M2khvj0XfNfCX801/6zlCz6W1wfWoJK6YQerKUMV1L", "X-Gm-Gg": "AeBDieun/Qgn81U+201IY1ThtZr7Y9G430jcPyU2uv7KPWBsjlEUJMDHc5d5HzfaEBY\n 4KkPI6t7RK26OGHu3xTzhNC0n6SjhQ+HUteKl/xfSXUWzShxTd/Skl6TrLWD+KJ1qCNYLCo/8kd\n 1CxoI7/JWupgYnNlBUTjF4i4JySvlgS6hxxNoJdpwQfmCpFYxAudvGGVpFmVfV5hrLvxdKQ4wty\n RvR0j4GXaKDEayvuU8BvYGLNbemM0wa5KmHOqi5eLkkJ+IWGxig1E4J59kR6vz04ec0bCuN4vxt\n 2CCp+pb9673MCAIuHx2sINB/FE4nKGbmv0/RbZd+khc7R18E/C42yIu4AXCvV6D3x+ZA/bCFDVl\n Q4mvgDvEjdIMFWKE9FNzHXNM3xjSevWasx95hsJF4TQyfnOGaX6DW1DJ075nY", "X-Received": [ "by 2002:a05:7301:1f17:b0:2ea:b975:3db1 with SMTP id\n 5a478bee46e88-2eab9753fd9mr8455408eec.23.1777129299045;\n Sat, 25 Apr 2026 08:01:39 -0700 (PDT)", "by 2002:a05:7301:1f17:b0:2ea:b975:3db1 with SMTP id\n 5a478bee46e88-2eab9753fd9mr8455383eec.23.1777129298077;\n Sat, 25 Apr 2026 08:01:38 -0700 (PDT)" ], "Content-Type": "multipart/mixed; boundary=\"------------z66Tz50pF4qlovDt0gM0CR9P\"", "Message-ID": "<73ee67db-86a3-4329-85e7-a7d5945687dc@oss.qualcomm.com>", "Date": "Sat, 25 Apr 2026 09:01:35 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "Subject": "[to-be-committed][RISC-V][PR target/123904] Improve bit masking of\n shifted values", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI1MDE1NSBTYWx0ZWRfX/BnozkJ9JsPi\n 7JV07n4YXMTF5+owg6nTKX1rIvCDjT97m8tzPctfU6NYZf4R5DwD/Bbb3EjGzNPhXNajhVNiIyz\n LQhtoGS/AxkzwZt8MK7hGBogH5y7eYeLrtcf4Zz/Xg4+AsK6+d+8YUJpNCBCoYdDPOZ4SGtR9nL\n X0s8Sh15wK0W3D+aXPuM1kYdFywmswng7EBlQu25mAJjqD328gVqjFBMHtgNn7S/xgtw5iDa1Eu\n EL9scElidKGF7IzHBbnHLVYSkfwXOxQaV3b5J1wrpI+pnDFxgr5HiuZQ0A6NjbsZ9dB0FFxFUkR\n GLcJ4TMKaDwxjHWe+wy4j8KD1voz+KCV4qBYl9JVj+whz2DDaV1CdvC/Beg0Mb/cJ6ch+MVo+2c\n 7lKjNsJCBwP3uAEk8eWzYC7pID0BqNDZDpU2WZGNelZpzQ32K1NAuLjpTEjfzOXIRPCZp3+uU3D\n K00Vk6xJ/PFZg7q9SZg==", "X-Proofpoint-ORIG-GUID": "lLFNu76RxTvMGF0PYhjXJZ4BEZGDSQEv", "X-Proofpoint-GUID": "lLFNu76RxTvMGF0PYhjXJZ4BEZGDSQEv", "X-Authority-Analysis": "v=2.4 cv=UcthjqSN c=1 sm=1 tr=0 ts=69ecd754 cx=c_pps\n a=Uww141gWH0fZj/3QKPojxA==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=9bxzY6XoPgeQoxKVDZEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=nSef5LCBrhb1KHXllC4A:9 a=B2y7HmGcmWMA:10 a=PxkB5W3o20Ba91AHUih5:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-25_04,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0\n adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604250155", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "If we are masking off bits on the upper and lower part of a register on \nriscv, depending on the precise mask it may be best implemented as a \nshift triplet. ie, shift left to clear upper bits, shift right to clear \nlower bits, shift left again to put the bits into their proper position.\n\nIf the input value is already left shifted and the shift count \ncorresponds to the low mask bits, then we can get away with just two \nshifts. We shift left to clear the relevant high bits, then shift right \nto put them into their proper position.\n\nThis likey came from spec or coremark given it was reported to me by the \nRAU team a while back. But the testcase didn't include enough \nbreadcrumbs to know for sure.\n\nThis has been repeatedly bootstrapped and regression tested on the \nPioneer and BPI as well as regularly regression tested on the \nriscv32-elf and riscv64-elf embedded targets.\n\nI'll wait for pre-commit CI to spin before pushing to the trunk.\n\n\nJeff\nPR target/123904\ngcc/\n\t* riscv.md (masking shifted value): New splitter to optimize\n\tcertain masking operations on shifted values.\n\ngcc/testsuite/\n\t* gcc.target/riscv/pr123904.c: New test.", "diff": "diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 7e9205fb24bf..6163023325d1 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -4995,6 +4995,35 @@ (define_split\n { operands[3] = GEN_INT (BITS_PER_WORD\n \t\t\t - exact_log2 (INTVAL (operands[3]) + 1)); })\n \n+;; This is similar using a shift triplet to implement a logical AND when\n+;; the mask is a consecutive_bits_operand.\n+;;\n+;; The difference is we have a left shift in the input RTL and we verify\n+;; that clears the appropriate low bits. So we can get away with just\n+;; two shifts.\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+\t(and:X (ashift:X (match_operand:X 1 \"register_operand\")\n+\t\t\t (match_operand 2 \"const_int_operand\"))\n+\t\t(match_operand 3 \"consecutive_bits_operand\")))\n+ (clobber (match_operand:X 4 \"register_operand\"))]\n+ \"ctz_hwi (INTVAL (operands[3]) & GET_MODE_MASK (word_mode)) == INTVAL (operands[2])\"\n+ [(set (match_dup 4) (ashift:X (match_dup 1) (match_dup 5)))\n+ (set (match_dup 0) (lshiftrt:X (match_dup 4) (match_dup 6)))]\n+\"{\n+ /* We want to left shift by the number of leading zeros in the mask,\n+ plus the number of bits shifted left by the pattern. Remember that\n+ a HOST_WIDE_INT may be 64 bits, so clz on that value can count bits\n+ we don't care about for rv32. */\n+ HOST_WIDE_INT lshift\n+ = clz_hwi (UINTVAL (operands[3])) % BITS_PER_WORD + INTVAL (operands[2]);\n+ operands[5] = gen_int_mode (lshift, QImode);\n+\n+ /* And then we right shift things back into position. */\n+ HOST_WIDE_INT rshift = lshift - INTVAL (operands[2]);\n+ operands[6] = gen_int_mode (rshift, QImode);\n+}\")\n+\n ;; Standard extensions and pattern for optimization\n (include \"bitmanip.md\")\n (include \"crypto.md\")\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr123904.c b/gcc/testsuite/gcc.target/riscv/pr123904.c\nnew file mode 100644\nindex 000000000000..7181c8de46f3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr123904.c\n@@ -0,0 +1,8 @@\n+/* { dg-do compile } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+unsigned foo19(unsigned a, unsigned b) { b = (b << 2) >> 2; return a + (b << 1); }\n+\n+/* { dg-final { scan-assembler-times \"slli\" 1 } } */\n+/* { dg-final { scan-assembler-times \"srli\" 1 } } */\n+/* { dg-final { scan-assembler-times \"add\" 1 } } */\n", "prefixes": [ "to-be-committed", "RISC-V", "PR", "target/123904" ] }