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GET /api/1.1/patches/2228151/?format=api
{ "id": 2228151, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228151/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260425131721.932250-11-joel@jms.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260425131721.932250-11-joel@jms.id.au>", "date": "2026-04-25T13:17:16", "name": "[v4,10/13] hw/riscv/atlantis: Add PCIe controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fd154463d55466a029fa1803a44b427683f55c50", "submitter": { "id": 48628, "url": "http://patchwork.ozlabs.org/api/1.1/people/48628/?format=api", "name": "Joel Stanley", "email": "joel@jms.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260425131721.932250-11-joel@jms.id.au/mbox/", "series": [ { "id": 501439, "url": "http://patchwork.ozlabs.org/api/1.1/series/501439/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501439", "date": "2026-04-25T13:17:08", "name": "hw/riscv: Add the Tenstorrent Atlantis machine", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/501439/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228151/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228151/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=q9znpy1D;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2r745gDTz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 25 Apr 2026 23:20:48 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wGcuU-0007To-WD; Sat, 25 Apr 2026 09:19:03 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wGcuT-0007Sd-3g\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:19:01 -0400", "from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wGcuQ-0000Hv-Hp\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:19:00 -0400", "by mail-pf1-x430.google.com with SMTP id\n d2e1a72fcca58-82f8cebc935so3831500b3a.0\n for <qemu-devel@nongnu.org>; Sat, 25 Apr 2026 06:18:58 -0700 (PDT)", "from donnager-debian.. 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helo=mail-pf1-x430.google.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicholas Piggin <npiggin@gmail.com>\n\nAtlantis has 3 DesignWare PCIe host controllers, however the boot firmware\nhas not been tested with the QEMU DesignWare model so a generic ECAM\ncontroller is used for the interim. The system bus aperture and PCIe IO\nmappings match the hardware configuration. Only a single PCIe controller is\nimplemented, because the gpex model does not support multiple controllers.\n\nBooting Linux v6.19:\n\n pci-host-generic 1110000000.pci: host bridge /soc/pci@1110000000 ranges:\n pci-host-generic 1110000000.pci: IO 0x30011000000..0x300110fffff -> 0x0000000000\n pci-host-generic 1110000000.pci: MEM 0x30080000000..0x300ffffffff -> 0x0080000000\n pci-host-generic 1110000000.pci: MEM 0x30100000000..0x3ff7fffffff -> 0x30100000000\n pci-host-generic 1110000000.pci: ECAM at [mem 0x1110000000-0x111fffffff] for [bus 00-ff]\n pci-host-generic 1110000000.pci: PCI host bridge to bus 0000:00\n pci_bus 0000:00: root bus resource [bus 00-ff]\n pci_bus 0000:00: root bus resource [io 0x0000-0xfffff]\n pci_bus 0000:00: root bus resource [mem 0x30080000000-0x300ffffffff] (bus address [0x80000000-0xffffffff])\n pci_bus 0000:00: root bus resource [mem 0x30100000000-0x3ff7fffffff pref]\n pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000 conventional PCI endpoint\n pci 0000:00:01.0: [1af4:1001] type 00 class 0x010000 conventional PCI endpoint\n pci 0000:00:01.0: BAR 0 [io 0x0000-0x007f]\n pci 0000:00:01.0: BAR 1 [mem 0x00000000-0x00000fff]\n pci 0000:00:01.0: BAR 4 [mem 0x00000000-0x00003fff 64bit pref]\n pci 0000:00:01.0: BAR 4 [mem 0x30100000000-0x30100003fff 64bit pref]: assigned\n pci 0000:00:01.0: BAR 1 [mem 0x30080000000-0x30080000fff]: assigned\n pci 0000:00:01.0: BAR 0 [io 0x0080-0x00ff]: assigned\n pci_bus 0000:00: resource 4 [io 0x0000-0xfffff]\n pci_bus 0000:00: resource 5 [mem 0x30080000000-0x300ffffffff]\n pci_bus 0000:00: resource 6 [mem 0x30100000000-0x3ff7fffffff pref]\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\nSigned-off-by: Joel Stanley <joel@jms.id.au>\n---\nv4:\n - Remove select PCI\n - Rework addressing, use a table for describing the map\n - Remove traces of controller 2 and 3; they will be implemented in\n future patches\nv3: Avoid leaks in the dt string allocation\n---\n include/hw/riscv/tt_atlantis.h | 12 ++\n hw/riscv/tt_atlantis.c | 234 ++++++++++++++++++++++++++++++++-\n hw/riscv/Kconfig | 1 +\n 3 files changed, 246 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h\nindex 9fe50d9c9040..070f53eeb450 100644\n--- a/include/hw/riscv/tt_atlantis.h\n+++ b/include/hw/riscv/tt_atlantis.h\n@@ -17,6 +17,13 @@\n #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME(\"tt-atlantis\")\n OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE)\n \n+typedef struct {\n+ hwaddr pcie_addr; /* Device side address */\n+ hwaddr window_offset; /* Host side offset */\n+ hwaddr size;\n+ uint32_t flags;\n+} PciMapEntry;\n+\n struct TTAtlantisState {\n /*< private >*/\n MachineState parent;\n@@ -25,9 +32,11 @@ struct TTAtlantisState {\n Notifier machine_done;\n FWCfgState *fw_cfg;\n const MemMapEntry *memmap;\n+ const PciMapEntry *pcimap;\n \n RISCVHartArrayState soc;\n DeviceState *irqchip;\n+ GPEXHost gpex_host;\n \n int fdt_size;\n };\n@@ -39,6 +48,7 @@ enum {\n TT_ATL_UART2_IRQ = 40,\n TT_ATL_UART3_IRQ = 41,\n TT_ATL_UART4_IRQ = 42,\n+ TT_ATL_PCIE0_INTA_IRQ = 96,\n };\n \n enum {\n@@ -50,6 +60,8 @@ enum {\n TT_ATL_I2C0,\n TT_ATL_MAPLIC,\n TT_ATL_MIMSIC,\n+ TT_ATL_PCIE_ECAM0,\n+ TT_ATL_PCIE_MMIO0,\n TT_ATL_SAPLIC,\n TT_ATL_SIMSIC,\n TT_ATL_SYSCON,\ndiff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c\nindex 5b66d7e95bb9..1eb473907ad7 100644\n--- a/hw/riscv/tt_atlantis.c\n+++ b/hw/riscv/tt_atlantis.c\n@@ -27,6 +27,7 @@\n #include \"hw/intc/riscv_aclint.h\"\n #include \"hw/intc/riscv_aplic.h\"\n #include \"hw/misc/pvpanic.h\"\n+#include \"hw/pci-host/gpex.h\"\n \n #include \"system/system.h\"\n #include \"system/device_tree.h\"\n@@ -51,6 +52,13 @@\n #define TT_ACLINT_MTIMECMP 0x8000\n #define TT_ACLINT_TIMEBASE_FREQ 1000000000\n \n+\n+enum {\n+ PCIE0_PIO,\n+ PCIE0_MMIO_32,\n+ PCIE0_MMIO_64,\n+};\n+\n static const MemMapEntry tt_atlantis_memmap[] = {\n /* Keep sorted with :'<,'>!sort -g -k 4 */\n [TT_ATL_DDR_LO] = { 0x00000000, 0x80000000 },\n@@ -66,6 +74,19 @@ static const MemMapEntry tt_atlantis_memmap[] = {\n [TT_ATL_MAPLIC] = { 0xcc000000, 0x4000000 },\n [TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 },\n [TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 },\n+ [TT_ATL_PCIE_ECAM0] = { 0x01110000000, 0x10000000 },\n+ [TT_ATL_PCIE_MMIO0] = { 0x30000000000, 0x10000000000 },\n+};\n+\n+static const PciMapEntry tt_atlantis_pci_map[] = {\n+ /* pcie_addr window_offset size flags */\n+ { 0x0, 0x11000000, 1 * MiB, FDT_PCI_RANGE_IOPORT |\n+ FDT_PCI_RANGE_RELOCATABLE },\n+ { 0x80000000, 0x80000000, 2 * GiB, FDT_PCI_RANGE_MMIO |\n+ FDT_PCI_RANGE_RELOCATABLE },\n+ { 0x30100000000, 0x100000000, 1018 * GiB, FDT_PCI_RANGE_MMIO_64BIT |\n+ FDT_PCI_RANGE_RELOCATABLE |\n+ FDT_PCI_RANGE_PREFETCHABLE },\n };\n \n static uint32_t next_phandle(void)\n@@ -74,6 +95,59 @@ static uint32_t next_phandle(void)\n return phandle++;\n }\n \n+static void create_pcie_irq_map(void *fdt, char *nodename, int legacy_irq,\n+ uint32_t irqchip_phandle)\n+{\n+ int pin, dev;\n+ uint32_t irq_map_stride = 0;\n+ uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS *\n+ FDT_MAX_INT_MAP_WIDTH] = {};\n+ uint32_t *irq_map = full_irq_map;\n+\n+ /*\n+ * This code creates a standard swizzle of interrupts such that\n+ * each device's first interrupt is based on it's PCI_SLOT number.\n+ * (See pci_swizzle_map_irq_fn())\n+ *\n+ * We only need one entry per interrupt in the table (not one per\n+ * possible slot) seeing the interrupt-map-mask will allow the table\n+ * to wrap to any number of devices.\n+ */\n+ for (dev = 0; dev < PCI_NUM_PINS; dev++) {\n+ int devfn = dev * 0x8;\n+\n+ for (pin = 0; pin < PCI_NUM_PINS; pin++) {\n+ int irq_nr = legacy_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);\n+ int i = 0;\n+\n+ /* Fill PCI address cells */\n+ irq_map[i] = cpu_to_be32(devfn << 8);\n+ i += FDT_PCI_ADDR_CELLS;\n+\n+ /* Fill PCI Interrupt cells */\n+ irq_map[i] = cpu_to_be32(pin + 1);\n+ i += FDT_PCI_INT_CELLS;\n+\n+ /* Fill interrupt controller phandle and cells */\n+ irq_map[i++] = cpu_to_be32(irqchip_phandle);\n+ irq_map[i++] = cpu_to_be32(irq_nr);\n+ irq_map[i++] = cpu_to_be32(0x4);\n+\n+ if (!irq_map_stride) {\n+ irq_map_stride = i;\n+ }\n+ irq_map += irq_map_stride;\n+ }\n+ }\n+\n+ qemu_fdt_setprop(fdt, nodename, \"interrupt-map\", full_irq_map,\n+ PCI_NUM_PINS * PCI_NUM_PINS *\n+ irq_map_stride * sizeof(uint32_t));\n+\n+ qemu_fdt_setprop_cells(fdt, nodename, \"interrupt-map-mask\",\n+ 0x1800, 0, 0, 0x7);\n+}\n+\n static void create_fdt_cpus(TTAtlantisState *s, uint32_t *intc_phandles)\n {\n uint32_t cpu_phandle;\n@@ -314,6 +388,52 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap,\n IRQ_S_EXT, s->soc.num_harts);\n }\n \n+static void create_fdt_pcie(void *fdt,\n+ const MemMapEntry *ecam_mem,\n+ const MemMapEntry *pcie_mem,\n+ const PciMapEntry *pio,\n+ const PciMapEntry *mmio32,\n+ const PciMapEntry *mmio64,\n+ int legacy_irq,\n+ uint32_t aplic_s_phandle,\n+ uint32_t imsic_s_phandle)\n+{\n+ g_autofree char *name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n+ ecam_mem->base);\n+\n+ qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", FDT_PCI_ADDR_CELLS);\n+ qemu_fdt_setprop_cell(fdt, name, \"#interrupt-cells\", FDT_PCI_INT_CELLS);\n+ qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0x2);\n+ qemu_fdt_setprop_string(fdt, name, \"compatible\", \"pci-host-ecam-generic\");\n+ qemu_fdt_setprop_string(fdt, name, \"device_type\", \"pci\");\n+ qemu_fdt_setprop_cells(fdt, name, \"bus-range\", 0,\n+ ecam_mem->size / PCIE_MMCFG_SIZE_MIN - 1);\n+ qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n+ qemu_fdt_setprop_cell(fdt, name, \"msi-parent\", imsic_s_phandle);\n+\n+ qemu_fdt_setprop_sized_cells(fdt, name, \"reg\",\n+ 2, ecam_mem->base,\n+ 2, ecam_mem->size);\n+\n+ qemu_fdt_setprop_sized_cells(fdt, name, \"ranges\",\n+ 1, pio->flags,\n+ 2, pio->pcie_addr,\n+ 2, pio->window_offset + pcie_mem->base,\n+ 2, pio->size,\n+\n+ 1, mmio32->flags,\n+ 2, mmio32->pcie_addr,\n+ 2, mmio32->window_offset + pcie_mem->base,\n+ 2, mmio32->size,\n+\n+ 1, mmio64->flags,\n+ 2, mmio64->pcie_addr,\n+ 2, mmio64->window_offset + pcie_mem->base,\n+ 2, mmio64->size);\n+\n+ create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle);\n+}\n+\n static void create_fdt_reset(void *fdt, const MemMapEntry *mem)\n {\n uint32_t syscon_phandle = next_phandle();\n@@ -379,6 +499,15 @@ static void finalize_fdt(TTAtlantisState *s)\n * aplic_s_phandle);\n */\n \n+ create_fdt_pcie(fdt,\n+ &s->memmap[TT_ATL_PCIE_ECAM0],\n+ &s->memmap[TT_ATL_PCIE_MMIO0],\n+ &s->pcimap[PCIE0_PIO],\n+ &s->pcimap[PCIE0_MMIO_32],\n+ &s->pcimap[PCIE0_MMIO_64],\n+ TT_ATL_PCIE0_INTA_IRQ,\n+ aplic_s_phandle, imsic_s_phandle);\n+\n create_fdt_reset(fdt, &s->memmap[TT_ATL_SYSCON]);\n \n create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ,\n@@ -389,7 +518,7 @@ static void create_fdt(TTAtlantisState *s)\n {\n MachineState *ms = MACHINE(s);\n uint8_t rng_seed[32];\n- g_autofree char *name = NULL;\n+ char *name;\n void *fdt;\n \n fdt = create_device_tree(&s->fdt_size);\n@@ -411,6 +540,15 @@ static void create_fdt(TTAtlantisState *s)\n qemu_fdt_setprop_cell(fdt, \"/soc\", \"#size-cells\", 0x2);\n qemu_fdt_setprop_cell(fdt, \"/soc\", \"#address-cells\", 0x2);\n \n+ /*\n+ * The \"/soc/pci@...\" node is needed for PCIE hotplugs\n+ * that might happen before finalize_fdt().\n+ */\n+ name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n+ s->memmap[TT_ATL_PCIE_ECAM0].base);\n+ qemu_fdt_add_subnode(fdt, name);\n+ g_free(name);\n+\n qemu_fdt_add_subnode(fdt, \"/chosen\");\n \n /* Pass seed to RNG */\n@@ -423,6 +561,95 @@ static void create_fdt(TTAtlantisState *s)\n create_fdt_pmu(s);\n }\n \n+static void gpex_pcie_init_one(TTAtlantisState *s, GPEXHost *gpex_host,\n+ MemoryRegion *mr,\n+ const MemMapEntry *ecam_mem,\n+ const MemMapEntry *pcie_mem,\n+ const PciMapEntry *mem_pio,\n+ const PciMapEntry *mem_mmio32,\n+ const PciMapEntry *mem_mmio64,\n+ int legacy_irq)\n+{\n+ DeviceState *dev;\n+ Object *obj;\n+ MemoryRegion *ecam_alias, *ecam_reg;\n+ MemoryRegion *mmio32_alias, *mmio64_alias, *mmio_reg;\n+ hwaddr ecam_base = ecam_mem->base;\n+ hwaddr ecam_size = ecam_mem->size;\n+ hwaddr pio_base = mem_pio->window_offset + pcie_mem->base;\n+ hwaddr pio_size = mem_pio->size;\n+ hwaddr mmio32_base = mem_mmio32->window_offset + pcie_mem->base;\n+ hwaddr mmio32_size = mem_mmio32->size;\n+ hwaddr mmio64_base = mem_mmio64->window_offset + pcie_mem->base;\n+ hwaddr mmio64_size = mem_mmio64->size;\n+ qemu_irq irq;\n+ char name[16];\n+ int i;\n+\n+ snprintf(name, sizeof(name), \"pcie\");\n+ object_initialize_child(OBJECT(s), name, gpex_host, TYPE_GPEX_HOST);\n+ dev = DEVICE(gpex_host);\n+ obj = OBJECT(dev);\n+\n+ object_property_set_uint(obj, PCI_HOST_ECAM_BASE, ecam_base, &error_abort);\n+ object_property_set_int(obj, PCI_HOST_ECAM_SIZE, ecam_size, &error_abort);\n+ object_property_set_uint(obj, PCI_HOST_BELOW_4G_MMIO_BASE, mmio32_base,\n+ &error_abort);\n+ object_property_set_int(obj, PCI_HOST_BELOW_4G_MMIO_SIZE, mmio32_size,\n+ &error_abort);\n+ object_property_set_uint(obj, PCI_HOST_ABOVE_4G_MMIO_BASE, mmio64_base,\n+ &error_abort);\n+ object_property_set_int(obj, PCI_HOST_ABOVE_4G_MMIO_SIZE, mmio64_size,\n+ &error_abort);\n+ object_property_set_uint(obj, PCI_HOST_PIO_BASE, pio_base, &error_abort);\n+ object_property_set_int(obj, PCI_HOST_PIO_SIZE, pio_size, &error_abort);\n+\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);\n+\n+ ecam_alias = g_new0(MemoryRegion, 1);\n+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);\n+ snprintf(name, sizeof(name), \"pcie.ecam\");\n+ memory_region_init_alias(ecam_alias, obj, name,\n+ ecam_reg, 0, ecam_size);\n+ memory_region_add_subregion(mr, ecam_base, ecam_alias);\n+\n+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);\n+\n+ mmio32_alias = g_new0(MemoryRegion, 1);\n+ snprintf(name, sizeof(name), \"pcie.mmio32\");\n+ memory_region_init_alias(mmio32_alias, obj, name,\n+ mmio_reg, mmio32_base & 0xffffffffUL, mmio32_size);\n+ memory_region_add_subregion(mr, mmio32_base, mmio32_alias);\n+\n+ mmio64_alias = g_new0(MemoryRegion, 1);\n+ snprintf(name, sizeof(name), \"pcie.mmio64\");\n+ memory_region_init_alias(mmio64_alias, obj, name,\n+ mmio_reg, mmio64_base, mmio64_size);\n+ memory_region_add_subregion(mr, mmio64_base, mmio64_alias);\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);\n+\n+ for (i = 0; i < PCI_NUM_PINS; i++) {\n+ irq = qdev_get_gpio_in(s->irqchip, legacy_irq + i);\n+\n+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);\n+ gpex_set_irq_num(GPEX_HOST(dev), i, legacy_irq + i);\n+ }\n+\n+ gpex_host->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus;\n+}\n+\n+static void gpex_pcie_init(TTAtlantisState *s, MemoryRegion *mr)\n+{\n+ gpex_pcie_init_one(s, &s->gpex_host, mr,\n+ &s->memmap[TT_ATL_PCIE_ECAM0],\n+ &s->memmap[TT_ATL_PCIE_MMIO0],\n+ &s->pcimap[PCIE0_PIO],\n+ &s->pcimap[PCIE0_MMIO_32],\n+ &s->pcimap[PCIE0_MMIO_64],\n+ TT_ATL_PCIE0_INTA_IRQ);\n+}\n+\n static DeviceState *create_reboot_device(const MemMapEntry *mem)\n {\n DeviceState *dev = qdev_new(TYPE_PVPANIC_MMIO_DEVICE);\n@@ -517,6 +744,7 @@ static void tt_atlantis_machine_init(MachineState *machine)\n int base_hartid = 0;\n \n s->memmap = tt_atlantis_memmap;\n+ s->pcimap = tt_atlantis_pci_map;\n \n object_initialize_child(OBJECT(machine), \"soc\", &s->soc,\n TYPE_RISCV_HART_ARRAY);\n@@ -582,6 +810,9 @@ static void tt_atlantis_machine_init(MachineState *machine)\n s->fw_cfg = create_fw_cfg(&s->memmap[TT_ATL_FW_CFG], machine->smp.cpus);\n rom_set_fw(s->fw_cfg);\n \n+ /* PCIe */\n+ gpex_pcie_init(s, system_memory);\n+\n /* Reboot and exit */\n create_reboot_device(&s->memmap[TT_ATL_SYSCON]);\n \n@@ -617,6 +848,7 @@ static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *data)\n mc->default_cpu_type = TYPE_RISCV_CPU_TT_ASCALON;\n mc->block_default_type = IF_VIRTIO;\n mc->no_cdrom = 1;\n+ mc->pci_allow_0_address = true;\n mc->default_ram_id = \"tt_atlantis.ram\";\n }\n \ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex 0601ae1a7494..f13a05c7b1d1 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -129,6 +129,7 @@ config TENSTORRENT\n select DEVICE_TREE\n select RISCV_NUMA\n select PVPANIC_MMIO\n+ select PCI_EXPRESS_GENERIC_BRIDGE\n select SERIAL_MM\n select RISCV_ACLINT\n select RISCV_APLIC\n", "prefixes": [ "v4", "10/13" ] }