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GET /api/1.1/patches/2228142/?format=api
{ "id": 2228142, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228142/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260425131721.932250-3-joel@jms.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260425131721.932250-3-joel@jms.id.au>", "date": "2026-04-25T13:17:08", "name": "[v4,02/13] hw/riscv/boot: Describe discontiguous memory in boot_info", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2702c3381f3c9646bfe44a1315e15e50c9bc3c1a", "submitter": { "id": 48628, "url": "http://patchwork.ozlabs.org/api/1.1/people/48628/?format=api", "name": "Joel Stanley", "email": "joel@jms.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260425131721.932250-3-joel@jms.id.au/mbox/", "series": [ { "id": 501439, "url": "http://patchwork.ozlabs.org/api/1.1/series/501439/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501439", "date": "2026-04-25T13:17:08", "name": "hw/riscv: Add the Tenstorrent Atlantis machine", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/501439/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228142/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228142/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=HNjll7B6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2r4r6lrkz1yJ2\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 25 Apr 2026 23:18:51 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wGctj-00070z-1s; Sat, 25 Apr 2026 09:18:15 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wGcte-00070G-UD\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:18:11 -0400", "from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wGctd-0008K6-Cv\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:18:10 -0400", "by mail-pf1-x429.google.com with SMTP id\n d2e1a72fcca58-82735a41920so3560117b3a.2\n for <qemu-devel@nongnu.org>; Sat, 25 Apr 2026 06:18:09 -0700 (PDT)", "from donnager-debian.. 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helo=mail-pf1-x429.google.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicholas Piggin <npiggin@gmail.com>\n\nMachines that have discontiguous memory may need to adjust where\nfirmware and images are loaded at boot. Provide an interface for\nmachines to describe a discontiguous low/high RAM scheme for this\npurpose.\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Joel Stanley <joel@jms.id.au>\n---\n include/hw/riscv/boot.h | 7 +++++++\n hw/riscv/boot.c | 11 +++++++++++\n 2 files changed, 18 insertions(+)", "diff": "diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\nindex f00b3ca12245..115e3222174f 100644\n--- a/include/hw/riscv/boot.h\n+++ b/include/hw/riscv/boot.h\n@@ -28,6 +28,10 @@\n #define RISCV64_BIOS_BIN \"opensbi-riscv64-generic-fw_dynamic.bin\"\n \n typedef struct RISCVBootInfo {\n+ /* First contiguous RAM region. If size is zero then assume entire RAM */\n+ hwaddr ram_low_start;\n+ hwaddr ram_low_size;\n+\n ssize_t kernel_size;\n hwaddr image_low_addr;\n hwaddr image_high_addr;\n@@ -43,6 +47,9 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);\n char *riscv_plic_hart_config_string(int hart_count);\n \n void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);\n+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n+ RISCVHartArrayState *harts,\n+ hwaddr start, hwaddr size);\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr);\n hwaddr riscv_find_and_load_firmware(MachineState *machine,\ndiff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\nindex 9086793b7a7b..5c9547429a36 100644\n--- a/hw/riscv/boot.c\n+++ b/hw/riscv/boot.c\n@@ -69,11 +69,22 @@ char *riscv_plic_hart_config_string(int hart_count)\n \n void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)\n {\n+ info->ram_low_start = 0;\n+ info->ram_low_size = 0;\n info->kernel_size = 0;\n info->initrd_size = 0;\n info->is_32bit = riscv_is_32bit(harts);\n }\n \n+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n+ RISCVHartArrayState *harts,\n+ hwaddr start, hwaddr size)\n+{\n+ riscv_boot_info_init(info, harts);\n+ info->ram_low_start = start;\n+ info->ram_low_size = size;\n+}\n+\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr) {\n if (info->is_32bit) {\n", "prefixes": [ "v4", "02/13" ] }