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GET /api/1.1/patches/2228006/?format=api
{ "id": 2228006, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228006/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424191129.1494381-4-daniel.barboza@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260424191129.1494381-4-daniel.barboza@oss.qualcomm.com>", "date": "2026-04-24T19:11:28", "name": "[v5,3/4] hw/riscv: server platform reference machine", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "305ebe830b31f0bdf4b3525591c61f653a2f1733", "submitter": { "id": 92288, "url": "http://patchwork.ozlabs.org/api/1.1/people/92288/?format=api", "name": "Daniel Henrique Barboza", "email": "daniel.barboza@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424191129.1494381-4-daniel.barboza@oss.qualcomm.com/mbox/", "series": [ { "id": 501400, "url": "http://patchwork.ozlabs.org/api/1.1/series/501400/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501400", "date": "2026-04-24T19:11:25", "name": "hw/riscv: Server Platform Reference Board", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501400/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228006/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228006/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n 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"Date": "Fri, 24 Apr 2026 16:11:28 -0300", "Message-ID": "<20260424191129.1494381-4-daniel.barboza@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com>", "References": "<20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI0MDE4NiBTYWx0ZWRfX9dEF3i3e/qI9\n 376GrIfVrfrZPf+WAPVeCFBNQ8in1cOxp+ZUhLVWmD7UChF9NrEmS8e/GWSGGax0z+dRAXuFx7M\n AraSdBoAOYx7tvVZH1MpZCTvhNvRv/tkjXycU/szexaLm/Jp82t7pNpIrTmYQCLRhvkDw+ixT57\n cPdoMOWy2K9Na13VUob8MGUhvLJh/LeCN6J/EAJXyaWZVEaoSc2j+5Gp+ktRaCQLbyw5Z50TsUU\n FW4xRTk2r7/4M1DIcdW7T9WFEn8Yhgga3cKns1Szk9kj/0r36Qm63iwObAqwQwbbJi22zlsDOG0\n ZQnKVPIEXsI4jmgJvz0tcvrPMU9Ir3YS/+PU119TEEDRR/jC0wFHLOG/4MPnL//XiwCUAr4wT6L\n GeCWIt6EOdQAeM+6BYYU1YvBGZzyF1icLVSu1VNWhS9dCWLhosvGwqO8eWTTb1YbrXwk+p0OKio\n F4/ckvUjy7ucrxRLd8g==", "X-Proofpoint-ORIG-GUID": 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reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240186", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=daniel.barboza@oss.qualcomm.com;\n helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Fei Wu <wu.fei9@sanechips.com.cn>\n\nThe RISC-V Server Platform specification [1] defines a standardized set\nof hardware and software capabilities, that portable system software,\nsuch as OS and hypervisors can rely on being present in a RISC-V server\nplatform.\n\nThe main features included in this emulation are:\n\n- Based on riscv virt machine type;\n- A new memory map as close as virt machine as possible;\n- An always present IOMMU platform device (riscv-iommu-sys) that uses\n IRQs 36 to 39, one IRQ for queue, similar to the 'virt' board;\n- AIA;\n- PCIe AHCI;\n- PCIe NIC;\n- No virtio device;\n- No fw_cfg device;\n- No ACPI table provided;\n- Only minimal device tree nodes.\n\n[1] https://github.com/riscv-non-isa/riscv-server-platform\n\nSigned-off-by: Fei Wu <wu.fei9@sanechips.com.cn>\nSigned-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\n---\n configs/devices/riscv64-softmmu/default.mak | 1 +\n hw/riscv/Kconfig | 15 +\n hw/riscv/meson.build | 1 +\n hw/riscv/server_platform_ref.c | 1371 +++++++++++++++++++\n 4 files changed, 1388 insertions(+)\n create mode 100644 hw/riscv/server_platform_ref.c", "diff": "diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/riscv64-softmmu/default.mak\nindex a8e4d0ab33..ae3f62e2d4 100644\n--- a/configs/devices/riscv64-softmmu/default.mak\n+++ b/configs/devices/riscv64-softmmu/default.mak\n@@ -9,6 +9,7 @@\n # CONFIG_SIFIVE_E=n\n # CONFIG_SIFIVE_U=n\n # CONFIG_RISCV_VIRT=n\n+# CONFIG_RISCV_SERVER_PLATFORM_REF=n\n # CONFIG_MICROCHIP_PFSOC=n\n # CONFIG_SHAKTI_C=n\n # CONFIG_XIANGSHAN_KUNMINGHU=n\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex 0222c93f87..acb3d2fa53 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -69,6 +69,21 @@ config RISCV_VIRT\n select ACPI\n select ACPI_PCI\n \n+config RISCV_SERVER_PLATFORM_REF\n+ bool\n+ default y\n+ depends on RISCV64\n+ select RISCV_NUMA\n+ select GOLDFISH_RTC\n+ select PCI\n+ select PCI_EXPRESS_GENERIC_BRIDGE\n+ select PFLASH_CFI01\n+ select SERIAL\n+ select RISCV_ACLINT\n+ select RISCV_APLIC\n+ select RISCV_IMSIC\n+ select RISCV_IOMMU\n+\n config SHAKTI_C\n bool\n default y\ndiff --git a/hw/riscv/meson.build b/hw/riscv/meson.build\nindex 533472e22a..74944cca84 100644\n--- a/hw/riscv/meson.build\n+++ b/hw/riscv/meson.build\n@@ -4,6 +4,7 @@ riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))\n riscv_ss.add(files('riscv_hart.c'))\n riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))\n riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))\n+riscv_ss.add(when: 'CONFIG_RISCV_SERVER_PLATFORM_REF', if_true: files('server_platform_ref.c'))\n riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))\n riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))\n riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))\ndiff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c\nnew file mode 100644\nindex 0000000000..bc74f8481c\n--- /dev/null\n+++ b/hw/riscv/server_platform_ref.c\n@@ -0,0 +1,1371 @@\n+/*\n+ * QEMU RISC-V Server Platform Reference Board (riscv-server-ref)\n+ *\n+ * Copyright (c) 2024 Intel, Inc.\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/units.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qemu/guest-random.h\"\n+#include \"qapi/error.h\"\n+#include \"qapi/qapi-visit-common.h\"\n+#include \"hw/core/boards.h\"\n+#include \"hw/core/loader.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"hw/char/serial.h\"\n+#include \"hw/block/flash.h\"\n+#include \"hw/ide/pci.h\"\n+#include \"hw/ide/ahci-pci.h\"\n+#include \"hw/pci/pci.h\"\n+#include \"hw/pci-host/gpex.h\"\n+#include \"hw/core/sysbus-fdt.h\"\n+#include \"hw/riscv/riscv_hart.h\"\n+#include \"hw/riscv/boot.h\"\n+#include \"hw/riscv/numa.h\"\n+#include \"hw/riscv/iommu.h\"\n+#include \"hw/riscv/riscv-iommu-bits.h\"\n+#include \"hw/intc/riscv_aclint.h\"\n+#include \"hw/intc/riscv_aplic.h\"\n+#include \"hw/intc/riscv_imsic.h\"\n+#include \"chardev/char.h\"\n+#include \"hw/char/serial-mm.h\"\n+#include \"system/device_tree.h\"\n+#include \"system/runstate.h\"\n+#include \"system/system.h\"\n+#include \"system/tcg.h\"\n+#include \"system/qtest.h\"\n+#include \"target/riscv/cpu.h\"\n+#include \"target/riscv/pmu.h\"\n+#include \"net/net.h\"\n+\n+#define RVSERVER_CPUS_MAX_BITS 9\n+#define RVSERVER_CPUS_MAX (1 << RVSERVER_CPUS_MAX_BITS)\n+#define RVSERVER_SOCKETS_MAX_BITS 2\n+#define RVSERVER_SOCKETS_MAX (1 << RVSERVER_SOCKETS_MAX_BITS)\n+\n+#define RVSERVER_IRQCHIP_NUM_MSIS 255\n+#define RVSERVER_IRQCHIP_NUM_SOURCES 96\n+#define RVSERVER_IRQCHIP_NUM_PRIO_BITS 3\n+#define RVSERVER_IRQCHIP_MAX_GUESTS_BITS 3\n+#define RVSERVER_IRQCHIP_MAX_GUESTS \\\n+ ((1U << RVSERVER_IRQCHIP_MAX_GUESTS_BITS) - 1U)\n+\n+#define FDT_PCI_ADDR_CELLS 3\n+#define FDT_PCI_INT_CELLS 1\n+#define FDT_APLIC_INT_CELLS 2\n+#define FDT_IMSIC_INT_CELLS 0\n+#define FDT_MAX_INT_CELLS 2\n+#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \\\n+ 1 + FDT_MAX_INT_CELLS)\n+#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \\\n+ 1 + FDT_APLIC_INT_CELLS)\n+\n+#define NUM_SATA_PORTS 6\n+\n+#define SYSCON_RESET 0x1\n+#define SYSCON_POWEROFF 0x2\n+\n+#define TYPE_RISCV_SERVER_REF_MACHINE MACHINE_TYPE_NAME(\"riscv-server-ref\")\n+OBJECT_DECLARE_SIMPLE_TYPE(RISCVServerRefMachineState, RISCV_SERVER_REF_MACHINE)\n+\n+struct RISCVServerRefMachineState {\n+ /*< private >*/\n+ MachineState parent;\n+\n+ /*< public >*/\n+ Notifier machine_done;\n+ RISCVHartArrayState soc[RVSERVER_SOCKETS_MAX];\n+ DeviceState *irqchip[RVSERVER_SOCKETS_MAX];\n+ PFlashCFI01 *flash[2];\n+\n+ int fdt_size;\n+ int aia_guests;\n+ const MemMapEntry *memmap;\n+};\n+\n+enum {\n+ RVSERVER_DEBUG,\n+ RVSERVER_MROM,\n+ RVSERVER_RESET_SYSCON,\n+ RVSERVER_RTC,\n+ RVSERVER_IOMMU_SYS,\n+ RVSERVER_ACLINT,\n+ RVSERVER_APLIC_M,\n+ RVSERVER_APLIC_S,\n+ RVSERVER_UART0,\n+ RVSERVER_IMSIC_M,\n+ RVSERVER_IMSIC_S,\n+ RVSERVER_FLASH,\n+ RVSERVER_DRAM,\n+ RVSERVER_PCIE_MMIO,\n+ RVSERVER_PCIE_PIO,\n+ RVSERVER_PCIE_ECAM,\n+ RVSERVER_PCIE_MMIO_HIGH\n+};\n+\n+enum {\n+ RVSERVER_UART0_IRQ = 10,\n+ RVSERVER_RTC_IRQ = 11,\n+ RVSERVER_PCIE_IRQ = 0x20, /* 32 to 35 */\n+ IOMMU_SYS_IRQ = 0x24 /* 36 to 39 */\n+};\n+\n+/*\n+ * The server soc reference machine physical address space used by some of the\n+ * devices namely ACLINT, APLIC and IMSIC depend on number of Sockets, number\n+ * of CPUs, and number of IMSIC guest files.\n+ *\n+ * Various limits defined by RVSERVER_SOCKETS_MAX_BITS, RVSERVER_CPUS_MAX_BITS,\n+ * and RVSERVER_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization of\n+ * server reference machine physical address space.\n+ */\n+\n+#define RVSERVER_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)\n+#if RVSERVER_IMSIC_GROUP_MAX_SIZE < \\\n+ IMSIC_GROUP_SIZE(RVSERVER_CPUS_MAX_BITS, RVSERVER_IRQCHIP_MAX_GUESTS_BITS)\n+#error \"Can't accomodate single IMSIC group in address space\"\n+#endif\n+\n+#define RVSERVER_IMSIC_MAX_SIZE (RVSERVER_SOCKETS_MAX * \\\n+ RVSERVER_IMSIC_GROUP_MAX_SIZE)\n+#if 0x4000000 < RVSERVER_IMSIC_MAX_SIZE\n+#error \"Can't accomodate all IMSIC groups in address space\"\n+#endif\n+\n+static const MemMapEntry rvserver_ref_memmap[] = {\n+ [RVSERVER_DEBUG] = { 0x0, 0x100 },\n+ [RVSERVER_MROM] = { 0x1000, 0xf000 },\n+ [RVSERVER_RESET_SYSCON] = { 0x100000, 0x1000 },\n+ [RVSERVER_RTC] = { 0x101000, 0x1000 },\n+ [RVSERVER_IOMMU_SYS] = { 0x102000, 0x1000 },\n+ [RVSERVER_ACLINT] = { 0x2000000, 0x10000 },\n+ [RVSERVER_PCIE_PIO] = { 0x3000000, 0x10000 },\n+ [RVSERVER_APLIC_M] = { 0xc000000, APLIC_SIZE(RVSERVER_CPUS_MAX) },\n+ [RVSERVER_APLIC_S] = { 0xd000000, APLIC_SIZE(RVSERVER_CPUS_MAX) },\n+ [RVSERVER_UART0] = { 0x10000000, 0x100 },\n+ [RVSERVER_FLASH] = { 0x20000000, 0x4000000 },\n+ [RVSERVER_IMSIC_M] = { 0x24000000, RVSERVER_IMSIC_MAX_SIZE },\n+ [RVSERVER_IMSIC_S] = { 0x28000000, RVSERVER_IMSIC_MAX_SIZE },\n+ [RVSERVER_PCIE_ECAM] = { 0x30000000, 0x10000000 },\n+ [RVSERVER_PCIE_MMIO] = { 0x40000000, 0x40000000 },\n+ [RVSERVER_DRAM] = { 0x80000000, 0xff80000000ull },\n+ [RVSERVER_PCIE_MMIO_HIGH] = { 0x10000000000ull, 0x10000000000ull },\n+};\n+\n+#define RVSERVER_FLASH_SECTOR_SIZE (256 * KiB)\n+\n+static PFlashCFI01 *rvserver_flash_create(RISCVServerRefMachineState *s,\n+ const char *name,\n+ const char *alias_prop_name)\n+{\n+ /*\n+ * Create a single flash device. We use the same parameters as\n+ * the flash devices on the ARM virt board.\n+ */\n+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);\n+\n+ qdev_prop_set_uint64(dev, \"sector-length\", RVSERVER_FLASH_SECTOR_SIZE);\n+ qdev_prop_set_uint8(dev, \"width\", 4);\n+ qdev_prop_set_uint8(dev, \"device-width\", 2);\n+ qdev_prop_set_bit(dev, \"big-endian\", false);\n+ qdev_prop_set_uint16(dev, \"id0\", 0x89);\n+ qdev_prop_set_uint16(dev, \"id1\", 0x18);\n+ qdev_prop_set_uint16(dev, \"id2\", 0x00);\n+ qdev_prop_set_uint16(dev, \"id3\", 0x00);\n+ qdev_prop_set_string(dev, \"name\", name);\n+\n+ object_property_add_child(OBJECT(s), name, OBJECT(dev));\n+ object_property_add_alias(OBJECT(s), alias_prop_name,\n+ OBJECT(dev), \"drive\");\n+\n+ return PFLASH_CFI01(dev);\n+}\n+\n+static void rvserver_flash_map(PFlashCFI01 *flash,\n+ hwaddr base, hwaddr size,\n+ MemoryRegion *sysmem)\n+{\n+ DeviceState *dev = DEVICE(flash);\n+\n+ assert(QEMU_IS_ALIGNED(size, RVSERVER_FLASH_SECTOR_SIZE));\n+ assert(size / RVSERVER_FLASH_SECTOR_SIZE <= UINT32_MAX);\n+ qdev_prop_set_uint32(dev, \"num-blocks\", size / RVSERVER_FLASH_SECTOR_SIZE);\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);\n+\n+ memory_region_add_subregion(sysmem, base,\n+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),\n+ 0));\n+}\n+\n+static void rvserver_flash_maps(RISCVServerRefMachineState *s,\n+ MemoryRegion *sysmem)\n+{\n+ hwaddr flashsize = rvserver_ref_memmap[RVSERVER_FLASH].size / 2;\n+ hwaddr flashbase = rvserver_ref_memmap[RVSERVER_FLASH].base;\n+\n+ rvserver_flash_map(s->flash[0], flashbase, flashsize, sysmem);\n+ rvserver_flash_map(s->flash[1], flashbase + flashsize, flashsize, sysmem);\n+}\n+\n+static void create_pcie_irq_map(RISCVServerRefMachineState *s,\n+ void *fdt, char *nodename,\n+ uint32_t irqchip_phandle)\n+{\n+ int pin, dev;\n+ uint32_t irq_map_stride = 0;\n+ uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS *\n+ FDT_MAX_INT_MAP_WIDTH] = {};\n+ uint32_t *irq_map = full_irq_map;\n+\n+ /*\n+ * This code creates a standard swizzle of interrupts such that\n+ * each device's first interrupt is based on it's PCI_SLOT number.\n+ * (See pci_swizzle_map_irq_fn())\n+ *\n+ * We only need one entry per interrupt in the table (not one per\n+ * possible slot) seeing the interrupt-map-mask will allow the table\n+ * to wrap to any number of devices.\n+ */\n+ for (dev = 0; dev < PCI_NUM_PINS; dev++) {\n+ int devfn = dev * 0x8;\n+\n+ for (pin = 0; pin < PCI_NUM_PINS; pin++) {\n+ int irq_nr = RVSERVER_PCIE_IRQ +\n+ ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);\n+ int i = 0;\n+\n+ /* Fill PCI address cells */\n+ irq_map[i] = cpu_to_be32(devfn << 8);\n+ i += FDT_PCI_ADDR_CELLS;\n+\n+ /* Fill PCI Interrupt cells */\n+ irq_map[i] = cpu_to_be32(pin + 1);\n+ i += FDT_PCI_INT_CELLS;\n+\n+ /* Fill interrupt controller phandle and cells */\n+ irq_map[i++] = cpu_to_be32(irqchip_phandle);\n+ irq_map[i++] = cpu_to_be32(irq_nr);\n+ irq_map[i++] = cpu_to_be32(0x4);\n+\n+ if (!irq_map_stride) {\n+ irq_map_stride = i;\n+ }\n+ irq_map += irq_map_stride;\n+ }\n+ }\n+\n+ qemu_fdt_setprop(fdt, nodename, \"interrupt-map\", full_irq_map,\n+ PCI_NUM_PINS * PCI_NUM_PINS *\n+ irq_map_stride * sizeof(uint32_t));\n+\n+ qemu_fdt_setprop_cells(fdt, nodename, \"interrupt-map-mask\",\n+ 0x1800, 0, 0, 0x7);\n+}\n+\n+static void create_fdt_socket_cpus(RISCVServerRefMachineState *s, int socket,\n+ char *clust_name, uint32_t *phandle,\n+ uint32_t *intc_phandles)\n+{\n+ int cpu;\n+ uint32_t cpu_phandle;\n+ MachineState *ms = MACHINE(s);\n+ bool is_32_bit = riscv_is_32bit(&s->soc[0]);\n+ int8_t satp_mode_max;\n+\n+ for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {\n+ RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];\n+ satp_mode_max = cpu_ptr->cfg.max_satp_mode;\n+ g_autofree char *cpu_name = NULL;\n+ g_autofree char *core_name = NULL;\n+ g_autofree char *intc_name = NULL;\n+ g_autofree char *sv_name = NULL;\n+\n+ cpu_phandle = (*phandle)++;\n+\n+ cpu_name = g_strdup_printf(\"/cpus/cpu@%d\",\n+ s->soc[socket].hartid_base + cpu);\n+ qemu_fdt_add_subnode(ms->fdt, cpu_name);\n+\n+ if (satp_mode_max != -1) {\n+ sv_name = g_strdup_printf(\"riscv,%s\",\n+ satp_mode_str(satp_mode_max, is_32_bit));\n+ qemu_fdt_setprop_string(ms->fdt, cpu_name, \"mmu-type\", sv_name);\n+ }\n+\n+ riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name);\n+\n+ if (cpu_ptr->cfg.ext_zicbom) {\n+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, \"riscv,cbom-block-size\",\n+ cpu_ptr->cfg.cbom_blocksize);\n+ }\n+\n+ if (cpu_ptr->cfg.ext_zicboz) {\n+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, \"riscv,cboz-block-size\",\n+ cpu_ptr->cfg.cboz_blocksize);\n+ }\n+\n+ if (cpu_ptr->cfg.ext_zicbop) {\n+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, \"riscv,cbop-block-size\",\n+ cpu_ptr->cfg.cbop_blocksize);\n+ }\n+\n+ qemu_fdt_setprop_string(ms->fdt, cpu_name, \"compatible\", \"riscv\");\n+ qemu_fdt_setprop_string(ms->fdt, cpu_name, \"status\", \"okay\");\n+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, \"reg\",\n+ s->soc[socket].hartid_base + cpu);\n+ qemu_fdt_setprop_string(ms->fdt, cpu_name, \"device_type\", \"cpu\");\n+ riscv_socket_fdt_write_id(ms, cpu_name, socket);\n+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, \"phandle\", cpu_phandle);\n+\n+ intc_phandles[cpu] = (*phandle)++;\n+\n+ intc_name = g_strdup_printf(\"%s/interrupt-controller\", cpu_name);\n+ qemu_fdt_add_subnode(ms->fdt, intc_name);\n+ qemu_fdt_setprop_cell(ms->fdt, intc_name, \"phandle\",\n+ intc_phandles[cpu]);\n+ qemu_fdt_setprop_string(ms->fdt, intc_name, \"compatible\",\n+ \"riscv,cpu-intc\");\n+ qemu_fdt_setprop(ms->fdt, intc_name, \"interrupt-controller\", NULL, 0);\n+ qemu_fdt_setprop_cell(ms->fdt, intc_name, \"#interrupt-cells\", 1);\n+\n+ core_name = g_strdup_printf(\"%s/core%d\", clust_name, cpu);\n+ qemu_fdt_add_subnode(ms->fdt, core_name);\n+ qemu_fdt_setprop_cell(ms->fdt, core_name, \"cpu\", cpu_phandle);\n+ }\n+}\n+\n+static void create_fdt_socket_memory(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap, int socket)\n+{\n+ g_autofree char *mem_name = NULL;\n+ hwaddr addr, size;\n+ MachineState *ms = MACHINE(s);\n+\n+ addr = memmap[RVSERVER_DRAM].base + riscv_socket_mem_offset(ms, socket);\n+ size = riscv_socket_mem_size(ms, socket);\n+ mem_name = g_strdup_printf(\"/memory@%\"HWADDR_PRIx, addr);\n+ qemu_fdt_add_subnode(ms->fdt, mem_name);\n+ qemu_fdt_setprop_cells(ms->fdt, mem_name, \"reg\",\n+ addr >> 32, addr, size >> 32, size);\n+ qemu_fdt_setprop_string(ms->fdt, mem_name, \"device_type\", \"memory\");\n+ riscv_socket_fdt_write_id(ms, mem_name, socket);\n+}\n+\n+static void create_fdt_socket_aclint(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap, int socket,\n+ uint32_t *intc_phandles)\n+{\n+ int cpu;\n+ g_autofree char *name = NULL;\n+ hwaddr addr, size;\n+ uint32_t aclint_cells_size;\n+ g_autofree uint32_t *aclint_mtimer_cells = NULL;\n+ MachineState *ms = MACHINE(s);\n+\n+ aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);\n+\n+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {\n+ aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);\n+ aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);\n+ }\n+ aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;\n+\n+ addr = memmap[RVSERVER_ACLINT].base +\n+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket;\n+ size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;\n+\n+ name = g_strdup_printf(\"/soc/mtimer@%\"HWADDR_PRIx, addr);\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\",\n+ \"riscv,aclint-mtimer\");\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"reg\",\n+ 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,\n+ 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,\n+ 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,\n+ 0x0, RISCV_ACLINT_DEFAULT_MTIME);\n+ qemu_fdt_setprop(ms->fdt, name, \"interrupts-extended\",\n+ aclint_mtimer_cells, aclint_cells_size);\n+ riscv_socket_fdt_write_id(ms, name, socket);\n+}\n+\n+static uint32_t imsic_num_bits(uint32_t count)\n+{\n+ uint32_t ret = 0;\n+\n+ while (BIT(ret) < count) {\n+ ret++;\n+ }\n+\n+ return ret;\n+}\n+\n+static void create_fdt_one_imsic(RISCVServerRefMachineState *s,\n+ hwaddr base_addr,\n+ uint32_t *intc_phandles,\n+ uint32_t msi_phandle,\n+ bool m_mode, uint32_t imsic_guest_bits)\n+{\n+ int cpu, socket;\n+ g_autofree char *imsic_name = NULL;\n+ MachineState *ms = MACHINE(s);\n+ int socket_count = riscv_socket_count(ms);\n+ uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size;\n+ g_autofree uint32_t *imsic_cells = NULL;\n+ g_autofree uint32_t *imsic_regs = NULL;\n+\n+ imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);\n+ imsic_regs = g_new0(uint32_t, socket_count * 4);\n+\n+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {\n+ imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);\n+ imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);\n+ }\n+\n+ imsic_max_hart_per_socket = 0;\n+ for (socket = 0; socket < socket_count; socket++) {\n+ imsic_addr = base_addr + socket * RVSERVER_IMSIC_GROUP_MAX_SIZE;\n+ imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *\n+ s->soc[socket].num_harts;\n+ imsic_regs[socket * 4 + 0] = 0;\n+ imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);\n+ imsic_regs[socket * 4 + 2] = 0;\n+ imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);\n+ if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {\n+ imsic_max_hart_per_socket = s->soc[socket].num_harts;\n+ }\n+ }\n+\n+ imsic_name = g_strdup_printf(\"/soc/imsics@%lx\", (unsigned long)base_addr);\n+ qemu_fdt_add_subnode(ms->fdt, imsic_name);\n+ qemu_fdt_setprop_string(ms->fdt, imsic_name,\n+ \"compatible\", \"riscv,imsics\");\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"#interrupt-cells\",\n+ FDT_IMSIC_INT_CELLS);\n+ qemu_fdt_setprop(ms->fdt, imsic_name, \"interrupt-controller\", NULL, 0);\n+ qemu_fdt_setprop(ms->fdt, imsic_name, \"msi-controller\", NULL, 0);\n+ qemu_fdt_setprop(ms->fdt, imsic_name, \"interrupts-extended\",\n+ imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);\n+ qemu_fdt_setprop(ms->fdt, imsic_name, \"reg\", imsic_regs,\n+ socket_count * sizeof(uint32_t) * 4);\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"riscv,num-ids\",\n+ RVSERVER_IRQCHIP_NUM_MSIS);\n+\n+ if (imsic_guest_bits) {\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"riscv,guest-index-bits\",\n+ imsic_guest_bits);\n+ }\n+\n+ if (socket_count > 1) {\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"riscv,hart-index-bits\",\n+ imsic_num_bits(imsic_max_hart_per_socket));\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"riscv,group-index-bits\",\n+ imsic_num_bits(socket_count));\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"riscv,group-index-shift\",\n+ IMSIC_MMIO_GROUP_MIN_SHIFT);\n+ }\n+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, \"phandle\", msi_phandle);\n+}\n+\n+static void create_fdt_imsic(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap,\n+ uint32_t *phandle, uint32_t *intc_phandles,\n+ uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)\n+{\n+ *msi_m_phandle = (*phandle)++;\n+ *msi_s_phandle = (*phandle)++;\n+\n+ /* M-level IMSIC node */\n+ create_fdt_one_imsic(s, memmap[RVSERVER_IMSIC_M].base, intc_phandles,\n+ *msi_m_phandle, true, 0);\n+\n+ /* S-level IMSIC node */\n+ create_fdt_one_imsic(s, memmap[RVSERVER_IMSIC_S].base, intc_phandles,\n+ *msi_s_phandle, false,\n+ imsic_num_bits(s->aia_guests + 1));\n+\n+}\n+\n+static void create_fdt_one_aplic(RISCVServerRefMachineState *s, int socket,\n+ unsigned long aplic_addr, uint32_t aplic_size,\n+ uint32_t msi_phandle,\n+ uint32_t *intc_phandles,\n+ uint32_t aplic_phandle,\n+ uint32_t aplic_child_phandle,\n+ bool m_mode, int num_harts)\n+{\n+ int cpu;\n+ g_autofree char *aplic_name = NULL;\n+ g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2);\n+ MachineState *ms = MACHINE(s);\n+\n+ aplic_cells = g_new0(uint32_t, num_harts * 2);\n+\n+ for (cpu = 0; cpu < num_harts; cpu++) {\n+ aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);\n+ aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);\n+ }\n+\n+ aplic_name = g_strdup_printf(\"/soc/aplic@%lx\", aplic_addr);\n+ qemu_fdt_add_subnode(ms->fdt, aplic_name);\n+ qemu_fdt_setprop_string(ms->fdt, aplic_name, \"compatible\", \"riscv,aplic\");\n+ qemu_fdt_setprop_cell(ms->fdt, aplic_name,\n+ \"#interrupt-cells\", FDT_APLIC_INT_CELLS);\n+ qemu_fdt_setprop(ms->fdt, aplic_name, \"interrupt-controller\", NULL, 0);\n+\n+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, \"msi-parent\", msi_phandle);\n+\n+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, \"reg\",\n+ 0x0, aplic_addr, 0x0, aplic_size);\n+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, \"riscv,num-sources\",\n+ RVSERVER_IRQCHIP_NUM_SOURCES);\n+\n+ if (aplic_child_phandle) {\n+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, \"riscv,children\",\n+ aplic_child_phandle);\n+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, \"riscv,delegate\",\n+ aplic_child_phandle, 0x1,\n+ RVSERVER_IRQCHIP_NUM_SOURCES);\n+ }\n+\n+ riscv_socket_fdt_write_id(ms, aplic_name, socket);\n+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, \"phandle\", aplic_phandle);\n+}\n+\n+static void create_fdt_socket_aplic(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap, int socket,\n+ uint32_t msi_m_phandle,\n+ uint32_t msi_s_phandle,\n+ uint32_t *phandle,\n+ uint32_t *intc_phandles,\n+ uint32_t *aplic_phandles,\n+ int num_harts)\n+{\n+ unsigned long aplic_addr;\n+ uint32_t aplic_m_phandle, aplic_s_phandle;\n+\n+ aplic_m_phandle = (*phandle)++;\n+ aplic_s_phandle = (*phandle)++;\n+\n+ /* M-level APLIC node */\n+ aplic_addr = memmap[RVSERVER_APLIC_M].base +\n+ memmap[RVSERVER_APLIC_M].size * socket;\n+ create_fdt_one_aplic(s, socket, aplic_addr, memmap[RVSERVER_APLIC_M].size,\n+ msi_m_phandle, intc_phandles,\n+ aplic_m_phandle, aplic_s_phandle,\n+ true, num_harts);\n+\n+ /* S-level APLIC node */\n+ aplic_addr = memmap[RVSERVER_APLIC_S].base +\n+ memmap[RVSERVER_APLIC_S].size * socket;\n+ create_fdt_one_aplic(s, socket, aplic_addr, memmap[RVSERVER_APLIC_S].size,\n+ msi_s_phandle, intc_phandles,\n+ aplic_s_phandle, 0,\n+ false, num_harts);\n+\n+ aplic_phandles[socket] = aplic_s_phandle;\n+}\n+\n+static void create_fdt_pmu(RISCVServerRefMachineState *s)\n+{\n+ g_autofree char *pmu_name = g_strdup_printf(\"/pmu\");\n+ MachineState *ms = MACHINE(s);\n+ RISCVCPU hart = s->soc[0].harts[0];\n+\n+ qemu_fdt_add_subnode(ms->fdt, pmu_name);\n+ qemu_fdt_setprop_string(ms->fdt, pmu_name, \"compatible\", \"riscv,pmu\");\n+ riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);\n+}\n+\n+static void create_fdt_sockets(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap,\n+ uint32_t *phandle,\n+ uint32_t *irq_mmio_phandle,\n+ uint32_t *irq_pcie_phandle,\n+ uint32_t *msi_pcie_phandle)\n+{\n+ int socket, phandle_pos;\n+ MachineState *ms = MACHINE(s);\n+ uint32_t msi_m_phandle = 0, msi_s_phandle = 0;\n+ uint32_t xplic_phandles[MAX_NODES];\n+ g_autofree uint32_t *intc_phandles = NULL;\n+ int socket_count = riscv_socket_count(ms);\n+\n+ qemu_fdt_add_subnode(ms->fdt, \"/cpus\");\n+ qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"timebase-frequency\",\n+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);\n+ qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"#size-cells\", 0x0);\n+ qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"#address-cells\", 0x1);\n+ qemu_fdt_add_subnode(ms->fdt, \"/cpus/cpu-map\");\n+\n+ intc_phandles = g_new0(uint32_t, ms->smp.cpus);\n+\n+ phandle_pos = ms->smp.cpus;\n+ for (socket = (socket_count - 1); socket >= 0; socket--) {\n+ g_autofree char *clust_name = NULL;\n+ phandle_pos -= s->soc[socket].num_harts;\n+\n+ clust_name = g_strdup_printf(\"/cpus/cpu-map/cluster%d\", socket);\n+ qemu_fdt_add_subnode(ms->fdt, clust_name);\n+\n+ create_fdt_socket_cpus(s, socket, clust_name, phandle,\n+ &intc_phandles[phandle_pos]);\n+\n+ create_fdt_socket_memory(s, memmap, socket);\n+\n+ create_fdt_socket_aclint(s, memmap, socket,\n+ &intc_phandles[phandle_pos]);\n+ }\n+\n+ create_fdt_imsic(s, memmap, phandle, intc_phandles,\n+ &msi_m_phandle, &msi_s_phandle);\n+ *msi_pcie_phandle = msi_s_phandle;\n+\n+ phandle_pos = ms->smp.cpus;\n+ for (socket = (socket_count - 1); socket >= 0; socket--) {\n+ phandle_pos -= s->soc[socket].num_harts;\n+\n+ create_fdt_socket_aplic(s, memmap, socket,\n+ msi_m_phandle, msi_s_phandle, phandle,\n+ &intc_phandles[phandle_pos],\n+ xplic_phandles,\n+ s->soc[socket].num_harts);\n+ }\n+\n+ for (socket = 0; socket < socket_count; socket++) {\n+ if (socket == 0) {\n+ *irq_mmio_phandle = xplic_phandles[socket];\n+ *irq_pcie_phandle = xplic_phandles[socket];\n+ }\n+ if (socket == 1) {\n+ *irq_pcie_phandle = xplic_phandles[socket];\n+ }\n+ }\n+\n+ riscv_socket_fdt_write_distance_matrix(ms);\n+}\n+\n+static void create_fdt_iommu_sys(RISCVServerRefMachineState *s,\n+ uint32_t irq_chip,\n+ uint32_t msi_phandle,\n+ uint32_t *iommu_sys_phandle)\n+{\n+ const char comp[] = \"riscv,iommu\";\n+ void *fdt = MACHINE(s)->fdt;\n+ uint32_t iommu_phandle;\n+ g_autofree char *iommu_node = NULL;\n+ hwaddr addr = s->memmap[RVSERVER_IOMMU_SYS].base;\n+ hwaddr size = s->memmap[RVSERVER_IOMMU_SYS].size;\n+ uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = {\n+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,\n+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,\n+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,\n+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,\n+ };\n+\n+ iommu_node = g_strdup_printf(\"/soc/iommu@%\"HWADDR_PRIx,\n+ s->memmap[RVSERVER_IOMMU_SYS].base);\n+ iommu_phandle = qemu_fdt_alloc_phandle(fdt);\n+ qemu_fdt_add_subnode(fdt, iommu_node);\n+\n+ qemu_fdt_setprop(fdt, iommu_node, \"compatible\", comp, sizeof(comp));\n+ qemu_fdt_setprop_cell(fdt, iommu_node, \"#iommu-cells\", 1);\n+ qemu_fdt_setprop_cell(fdt, iommu_node, \"phandle\", iommu_phandle);\n+\n+ qemu_fdt_setprop_cells(fdt, iommu_node, \"reg\",\n+ addr >> 32, addr, size >> 32, size);\n+ qemu_fdt_setprop_cell(fdt, iommu_node, \"interrupt-parent\", irq_chip);\n+\n+ qemu_fdt_setprop_cells(fdt, iommu_node, \"interrupts\",\n+ iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,\n+ iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,\n+ iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,\n+ iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);\n+\n+ qemu_fdt_setprop_cell(fdt, iommu_node, \"msi-parent\", msi_phandle);\n+\n+ *iommu_sys_phandle = iommu_phandle;\n+}\n+\n+static void create_fdt_pcie(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap,\n+ uint32_t irq_pcie_phandle,\n+ uint32_t msi_pcie_phandle,\n+ uint32_t iommu_sys_phandle)\n+{\n+ g_autofree char *name = NULL;\n+ MachineState *ms = MACHINE(s);\n+\n+ name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIx,\n+ memmap[RVSERVER_PCIE_ECAM].base);\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"#address-cells\",\n+ FDT_PCI_ADDR_CELLS);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"#interrupt-cells\",\n+ FDT_PCI_INT_CELLS);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"#size-cells\", 0x2);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\",\n+ \"pci-host-ecam-generic\");\n+ qemu_fdt_setprop_string(ms->fdt, name, \"device_type\", \"pci\");\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"linux,pci-domain\", 0);\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"bus-range\", 0,\n+ memmap[RVSERVER_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);\n+ qemu_fdt_setprop(ms->fdt, name, \"dma-coherent\", NULL, 0);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"msi-parent\", msi_pcie_phandle);\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"reg\", 0,\n+ memmap[RVSERVER_PCIE_ECAM].base, 0, memmap[RVSERVER_PCIE_ECAM].size);\n+ qemu_fdt_setprop_sized_cells(ms->fdt, name, \"ranges\",\n+ 1, FDT_PCI_RANGE_IOPORT, 2, 0,\n+ 2, memmap[RVSERVER_PCIE_PIO].base, 2, memmap[RVSERVER_PCIE_PIO].size,\n+ 1, FDT_PCI_RANGE_MMIO,\n+ 2, memmap[RVSERVER_PCIE_MMIO].base,\n+ 2, memmap[RVSERVER_PCIE_MMIO].base, 2, memmap[RVSERVER_PCIE_MMIO].size,\n+ 1, FDT_PCI_RANGE_MMIO_64BIT,\n+ 2, memmap[RVSERVER_PCIE_MMIO_HIGH].base,\n+ 2, memmap[RVSERVER_PCIE_MMIO_HIGH].base, 2,\n+ memmap[RVSERVER_PCIE_MMIO_HIGH].size);\n+\n+ create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);\n+\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"iommu-map\",\n+ 0, iommu_sys_phandle, 0, 0, 0,\n+ iommu_sys_phandle, 0, 0xffff);\n+}\n+\n+static void create_fdt_reset(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap,\n+ uint32_t *phandle)\n+{\n+ char *name;\n+ uint32_t test_phandle;\n+ MachineState *ms = MACHINE(s);\n+\n+ test_phandle = (*phandle)++;\n+ name = g_strdup_printf(\"/soc/reset_syscon@%\"HWADDR_PRIx,\n+ memmap[RVSERVER_RESET_SYSCON].base);\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\", \"syscon\");\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"reg\",\n+ 0x0, memmap[RVSERVER_RESET_SYSCON].base,\n+ 0x0, memmap[RVSERVER_RESET_SYSCON].size);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"phandle\", test_phandle);\n+ test_phandle = qemu_fdt_get_phandle(ms->fdt, name);\n+ g_free(name);\n+\n+ name = g_strdup_printf(\"/soc/reboot\");\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\", \"syscon-reboot\");\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"regmap\", test_phandle);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"offset\", 0x0);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"value\", SYSCON_RESET);\n+ g_free(name);\n+\n+ name = g_strdup_printf(\"/soc/poweroff\");\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\", \"syscon-poweroff\");\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"regmap\", test_phandle);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"offset\", 0x0);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"value\", SYSCON_POWEROFF);\n+ g_free(name);\n+}\n+\n+static void create_fdt_uart(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap,\n+ uint32_t irq_mmio_phandle)\n+{\n+ g_autofree char *name = NULL;\n+ MachineState *ms = MACHINE(s);\n+\n+ name = g_strdup_printf(\"/soc/serial@%\"HWADDR_PRIx,\n+ memmap[RVSERVER_UART0].base);\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\", \"ns16550a\");\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"reg\",\n+ 0x0, memmap[RVSERVER_UART0].base,\n+ 0x0, memmap[RVSERVER_UART0].size);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"clock-frequency\", 3686400);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"interrupt-parent\",\n+ irq_mmio_phandle);\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"interrupts\",\n+ RVSERVER_UART0_IRQ, 0x4);\n+\n+ qemu_fdt_setprop_string(ms->fdt, \"/chosen\", \"stdout-path\", name);\n+}\n+\n+static void create_fdt_rtc(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap,\n+ uint32_t irq_mmio_phandle)\n+{\n+ g_autofree char *name = NULL;\n+ MachineState *ms = MACHINE(s);\n+\n+ name = g_strdup_printf(\"/soc/rtc@%\"HWADDR_PRIx,\n+ memmap[RVSERVER_RTC].base);\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\",\n+ \"google,goldfish-rtc\");\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"reg\",\n+ 0x0, memmap[RVSERVER_RTC].base, 0x0, memmap[RVSERVER_RTC].size);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"interrupt-parent\",\n+ irq_mmio_phandle);\n+ qemu_fdt_setprop_cells(ms->fdt, name, \"interrupts\",\n+ RVSERVER_RTC_IRQ, 0x4);\n+}\n+\n+static void create_fdt_flash(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap)\n+{\n+ MachineState *ms = MACHINE(s);\n+ hwaddr flashsize = rvserver_ref_memmap[RVSERVER_FLASH].size / 2;\n+ hwaddr flashbase = rvserver_ref_memmap[RVSERVER_FLASH].base;\n+ g_autofree char *name = g_strdup_printf(\"/flash@%\"HWADDR_PRIx, flashbase);\n+\n+ qemu_fdt_add_subnode(ms->fdt, name);\n+ qemu_fdt_setprop_string(ms->fdt, name, \"compatible\", \"cfi-flash\");\n+ qemu_fdt_setprop_sized_cells(ms->fdt, name, \"reg\",\n+ 2, flashbase, 2, flashsize,\n+ 2, flashbase + flashsize, 2, flashsize);\n+ qemu_fdt_setprop_cell(ms->fdt, name, \"bank-width\", 4);\n+}\n+\n+static void finalize_fdt(RISCVServerRefMachineState *s)\n+{\n+ uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;\n+ uint32_t irq_pcie_phandle = 1, iommu_sys_phandle;\n+\n+ create_fdt_sockets(s, rvserver_ref_memmap, &phandle, &irq_mmio_phandle,\n+ &irq_pcie_phandle, &msi_pcie_phandle);\n+\n+ create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,\n+ &iommu_sys_phandle);\n+\n+ create_fdt_pcie(s, rvserver_ref_memmap, irq_pcie_phandle,\n+ msi_pcie_phandle, iommu_sys_phandle);\n+\n+ create_fdt_reset(s, rvserver_ref_memmap, &phandle);\n+\n+ create_fdt_uart(s, rvserver_ref_memmap, irq_mmio_phandle);\n+\n+ create_fdt_rtc(s, rvserver_ref_memmap, irq_mmio_phandle);\n+}\n+\n+static void create_fdt(RISCVServerRefMachineState *s,\n+ const MemMapEntry *memmap)\n+{\n+ MachineState *ms = MACHINE(s);\n+ uint8_t rng_seed[32];\n+\n+ ms->fdt = create_device_tree(&s->fdt_size);\n+ if (!ms->fdt) {\n+ error_report(\"create_device_tree() failed\");\n+ exit(1);\n+ }\n+\n+ qemu_fdt_setprop_string(ms->fdt, \"/\", \"model\", \"qemu,riscv-server-ref\");\n+ qemu_fdt_setprop_string(ms->fdt, \"/\", \"compatible\", \"riscv-server-ref\");\n+ qemu_fdt_setprop_cell(ms->fdt, \"/\", \"#size-cells\", 0x2);\n+ qemu_fdt_setprop_cell(ms->fdt, \"/\", \"#address-cells\", 0x2);\n+\n+ /*\n+ * This versioning scheme is for informing platform fw only. It is neither:\n+ * - A QEMU versioned machine type; a given version of QEMU will emulate\n+ * a given version of the platform.\n+ * - A reflection of level of server platform support provided.\n+ *\n+ * machine-version-major: updated when changes breaking fw compatibility\n+ * are introduced.\n+ * machine-version-minor: updated when features are added that don't break\n+ * fw compatibility.\n+ *\n+ * It's the same as the scheme in arm sbsa-ref.\n+ */\n+ qemu_fdt_setprop_cell(ms->fdt, \"/\", \"machine-version-major\", 0);\n+ qemu_fdt_setprop_cell(ms->fdt, \"/\", \"machine-version-minor\", 0);\n+\n+ qemu_fdt_add_subnode(ms->fdt, \"/soc\");\n+ qemu_fdt_setprop(ms->fdt, \"/soc\", \"ranges\", NULL, 0);\n+ qemu_fdt_setprop_string(ms->fdt, \"/soc\", \"compatible\", \"simple-bus\");\n+ qemu_fdt_setprop_cell(ms->fdt, \"/soc\", \"#size-cells\", 0x2);\n+ qemu_fdt_setprop_cell(ms->fdt, \"/soc\", \"#address-cells\", 0x2);\n+\n+ qemu_fdt_add_subnode(ms->fdt, \"/chosen\");\n+\n+ /* Pass seed to RNG */\n+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));\n+ qemu_fdt_setprop(ms->fdt, \"/chosen\", \"rng-seed\",\n+ rng_seed, sizeof(rng_seed));\n+\n+ create_fdt_flash(s, memmap);\n+ create_fdt_pmu(s);\n+\n+}\n+\n+static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,\n+ DeviceState *irqchip,\n+ RISCVServerRefMachineState *s)\n+{\n+ DeviceState *dev;\n+ PCIHostState *pci;\n+ PCIDevice *pdev_ahci;\n+ AHCIPCIState *ich9;\n+ DriveInfo *hd[NUM_SATA_PORTS];\n+ MemoryRegion *ecam_alias, *ecam_reg;\n+ MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;\n+ hwaddr ecam_base = rvserver_ref_memmap[RVSERVER_PCIE_ECAM].base;\n+ hwaddr ecam_size = rvserver_ref_memmap[RVSERVER_PCIE_ECAM].size;\n+ hwaddr mmio_base = rvserver_ref_memmap[RVSERVER_PCIE_MMIO].base;\n+ hwaddr mmio_size = rvserver_ref_memmap[RVSERVER_PCIE_MMIO].size;\n+ hwaddr high_mmio_base = rvserver_ref_memmap[RVSERVER_PCIE_MMIO_HIGH].base;\n+ hwaddr high_mmio_size = rvserver_ref_memmap[RVSERVER_PCIE_MMIO_HIGH].size;\n+ hwaddr pio_base = rvserver_ref_memmap[RVSERVER_PCIE_PIO].base;\n+ hwaddr pio_size = rvserver_ref_memmap[RVSERVER_PCIE_PIO].size;\n+ MachineClass *mc = MACHINE_GET_CLASS(s);\n+ qemu_irq irq;\n+ int i;\n+\n+ dev = qdev_new(TYPE_GPEX_HOST);\n+\n+ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,\n+ ecam_base, NULL);\n+ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,\n+ ecam_size, NULL);\n+ object_property_set_uint(OBJECT(GPEX_HOST(dev)),\n+ PCI_HOST_BELOW_4G_MMIO_BASE,\n+ mmio_base, NULL);\n+ object_property_set_int(OBJECT(GPEX_HOST(dev)),\n+ PCI_HOST_BELOW_4G_MMIO_SIZE,\n+ mmio_size, NULL);\n+ object_property_set_uint(OBJECT(GPEX_HOST(dev)),\n+ PCI_HOST_ABOVE_4G_MMIO_BASE,\n+ high_mmio_base, NULL);\n+ object_property_set_int(OBJECT(GPEX_HOST(dev)),\n+ PCI_HOST_ABOVE_4G_MMIO_SIZE,\n+ high_mmio_size, NULL);\n+ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,\n+ pio_base, NULL);\n+ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,\n+ pio_size, NULL);\n+\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);\n+\n+ ecam_alias = g_new0(MemoryRegion, 1);\n+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);\n+ memory_region_init_alias(ecam_alias, OBJECT(dev), \"pcie-ecam\",\n+ ecam_reg, 0, ecam_size);\n+ memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);\n+\n+ mmio_alias = g_new0(MemoryRegion, 1);\n+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);\n+ memory_region_init_alias(mmio_alias, OBJECT(dev), \"pcie-mmio\",\n+ mmio_reg, mmio_base, mmio_size);\n+ memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);\n+\n+ /* Map high MMIO space */\n+ high_mmio_alias = g_new0(MemoryRegion, 1);\n+ memory_region_init_alias(high_mmio_alias, OBJECT(dev), \"pcie-mmio-high\",\n+ mmio_reg, high_mmio_base, high_mmio_size);\n+ memory_region_add_subregion(get_system_memory(), high_mmio_base,\n+ high_mmio_alias);\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);\n+\n+ for (i = 0; i < PCI_NUM_PINS; i++) {\n+ irq = qdev_get_gpio_in(irqchip, RVSERVER_PCIE_IRQ + i);\n+\n+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);\n+ gpex_set_irq_num(GPEX_HOST(dev), i, RVSERVER_PCIE_IRQ + i);\n+ }\n+\n+ pci = PCI_HOST_BRIDGE(dev);\n+ pci_init_nic_devices(pci->bus, mc->default_nic);\n+ /* IDE disk setup. */\n+ pdev_ahci = pci_create_simple(pci->bus, -1, TYPE_ICH9_AHCI);\n+ ich9 = ICH9_AHCI(pdev_ahci);\n+ g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports);\n+ ide_drive_get(hd, ich9->ahci.ports);\n+ ahci_ide_create_devs(&ich9->ahci, hd);\n+\n+ GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;\n+ return dev;\n+}\n+\n+static DeviceState *rvserver_ref_create_aia(int aia_guests,\n+ const MemMapEntry *memmap,\n+ int socket,\n+ int base_hartid, int hart_count)\n+{\n+ int i;\n+ hwaddr addr;\n+ uint32_t guest_bits;\n+ DeviceState *aplic_s = NULL;\n+ DeviceState *aplic_m = NULL;\n+ bool msimode = true;\n+\n+ /* Per-socket M-level IMSICs */\n+ addr = memmap[RVSERVER_IMSIC_M].base +\n+ socket * RVSERVER_IMSIC_GROUP_MAX_SIZE;\n+ for (i = 0; i < hart_count; i++) {\n+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),\n+ base_hartid + i, true, 1,\n+ RVSERVER_IRQCHIP_NUM_MSIS);\n+ }\n+\n+ /* Per-socket S-level IMSICs */\n+ guest_bits = imsic_num_bits(aia_guests + 1);\n+ addr = memmap[RVSERVER_IMSIC_S].base +\n+ socket * RVSERVER_IMSIC_GROUP_MAX_SIZE;\n+ for (i = 0; i < hart_count; i++) {\n+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),\n+ base_hartid + i, false, 1 + aia_guests,\n+ RVSERVER_IRQCHIP_NUM_MSIS);\n+ }\n+\n+ /* Per-socket M-level APLIC */\n+ aplic_m = riscv_aplic_create(memmap[RVSERVER_APLIC_M].base +\n+ socket * memmap[RVSERVER_APLIC_M].size,\n+ memmap[RVSERVER_APLIC_M].size,\n+ (msimode) ? 0 : base_hartid,\n+ (msimode) ? 0 : hart_count,\n+ RVSERVER_IRQCHIP_NUM_SOURCES,\n+ RVSERVER_IRQCHIP_NUM_PRIO_BITS,\n+ msimode, true, NULL);\n+\n+ /* Per-socket S-level APLIC */\n+ aplic_s = riscv_aplic_create(memmap[RVSERVER_APLIC_S].base +\n+ socket * memmap[RVSERVER_APLIC_S].size,\n+ memmap[RVSERVER_APLIC_S].size,\n+ (msimode) ? 0 : base_hartid,\n+ (msimode) ? 0 : hart_count,\n+ RVSERVER_IRQCHIP_NUM_SOURCES,\n+ RVSERVER_IRQCHIP_NUM_PRIO_BITS,\n+ msimode, false, aplic_m);\n+\n+ (void)aplic_s;\n+ return aplic_m;\n+}\n+\n+static uint64_t rvserver_reset_syscon_read(void *opaque, hwaddr addr,\n+ unsigned size)\n+{\n+ return 0;\n+}\n+\n+static void rvserver_reset_syscon_write(void *opaque, hwaddr addr,\n+ uint64_t val64, unsigned int size)\n+{\n+ switch (val64) {\n+ case SYSCON_POWEROFF:\n+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);\n+ return;\n+ case SYSCON_RESET:\n+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n+ return;\n+ default:\n+ break;\n+ }\n+}\n+\n+static const MemoryRegionOps rvserver_reset_syscon_ops = {\n+ .read = rvserver_reset_syscon_read,\n+ .write = rvserver_reset_syscon_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN\n+};\n+\n+static void rvserver_ref_machine_done(Notifier *notifier, void *data)\n+{\n+ RISCVServerRefMachineState *s = container_of(\n+ notifier, RISCVServerRefMachineState, machine_done);\n+ const MemMapEntry *memmap = rvserver_ref_memmap;\n+ MachineState *machine = MACHINE(s);\n+ hwaddr start_addr = memmap[RVSERVER_DRAM].base;\n+ target_ulong firmware_end_addr, kernel_start_addr;\n+ const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);\n+ uint64_t fdt_load_addr;\n+ uint64_t kernel_entry = 0;\n+ BlockBackend *pflash_blk0;\n+ RISCVBootInfo boot_info;\n+\n+ /*\n+ * An user provided dtb must include everything, including\n+ * dynamic sysbus devices. Our FDT needs to be finalized.\n+ */\n+ if (machine->dtb == NULL) {\n+ finalize_fdt(s);\n+ }\n+\n+ firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,\n+ &start_addr, NULL);\n+\n+ pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);\n+ if (pflash_blk0) {\n+ if (machine->firmware && !strcmp(machine->firmware, \"none\")) {\n+ /*\n+ * Pflash was supplied but bios is none and not KVM guest,\n+ * let's overwrite the address we jump to after reset to\n+ * the base of the flash.\n+ */\n+ start_addr = rvserver_ref_memmap[RVSERVER_FLASH].base;\n+ } else {\n+ /*\n+ * Pflash was supplied but either KVM guest or bios is not none.\n+ * In this case, base of the flash would contain S-mode payload.\n+ */\n+ riscv_setup_firmware_boot(machine);\n+ kernel_entry = rvserver_ref_memmap[RVSERVER_FLASH].base;\n+ }\n+ }\n+\n+ riscv_boot_info_init(&boot_info, &s->soc[0]);\n+\n+ if (machine->kernel_filename && !kernel_entry) {\n+ kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,\n+ firmware_end_addr);\n+ riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NULL);\n+ kernel_entry = boot_info.image_low_addr;\n+ }\n+\n+ fdt_load_addr = riscv_compute_fdt_addr(memmap[RVSERVER_DRAM].base,\n+ memmap[RVSERVER_DRAM].size,\n+ machine, &boot_info);\n+\n+ riscv_load_fdt(fdt_load_addr, machine->fdt);\n+\n+ /* load the reset vector */\n+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,\n+ rvserver_ref_memmap[RVSERVER_MROM].base,\n+ rvserver_ref_memmap[RVSERVER_MROM].size,\n+ kernel_entry,\n+ fdt_load_addr);\n+\n+}\n+\n+static bool rvserver_aclint_allowed(void)\n+{\n+ return tcg_enabled() || qtest_enabled();\n+}\n+\n+static void rvserver_ref_machine_init(MachineState *machine)\n+{\n+ const MemMapEntry *memmap = rvserver_ref_memmap;\n+ RISCVServerRefMachineState *s = RISCV_SERVER_REF_MACHINE(machine);\n+ MemoryRegion *system_memory = get_system_memory();\n+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);\n+ MemoryRegion *reset_syscon_io = g_new(MemoryRegion, 1);\n+ DeviceState *mmio_irqchip, *pcie_irqchip, *iommu_sys;\n+ int i, base_hartid, hart_count;\n+ int socket_count = riscv_socket_count(machine);\n+\n+ /* Check socket count limit */\n+ if (RVSERVER_SOCKETS_MAX < socket_count) {\n+ error_report(\"number of sockets/nodes should be less than %d\",\n+ RVSERVER_SOCKETS_MAX);\n+ exit(1);\n+ }\n+\n+ if (!rvserver_aclint_allowed()) {\n+ error_report(\"'aclint' is only available with TCG acceleration\");\n+ exit(1);\n+ }\n+\n+ /* Initialize sockets */\n+ mmio_irqchip = pcie_irqchip = NULL;\n+ for (i = 0; i < socket_count; i++) {\n+ g_autofree char *soc_name = g_strdup_printf(\"soc%d\", i);\n+\n+ if (!riscv_socket_check_hartids(machine, i)) {\n+ error_report(\"discontinuous hartids in socket%d\", i);\n+ exit(1);\n+ }\n+\n+ base_hartid = riscv_socket_first_hartid(machine, i);\n+ if (base_hartid < 0) {\n+ error_report(\"can't find hartid base for socket%d\", i);\n+ exit(1);\n+ }\n+\n+ hart_count = riscv_socket_hart_count(machine, i);\n+ if (hart_count < 0) {\n+ error_report(\"can't find hart count for socket%d\", i);\n+ exit(1);\n+ }\n+\n+ object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],\n+ TYPE_RISCV_HART_ARRAY);\n+ object_property_set_str(OBJECT(&s->soc[i]), \"cpu-type\",\n+ machine->cpu_type, &error_abort);\n+ object_property_set_int(OBJECT(&s->soc[i]), \"hartid-base\",\n+ base_hartid, &error_abort);\n+ object_property_set_int(OBJECT(&s->soc[i]), \"num-harts\",\n+ hart_count, &error_abort);\n+ sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);\n+\n+ /* Per-socket ACLINT MTIMER */\n+ riscv_aclint_mtimer_create(memmap[RVSERVER_ACLINT].base +\n+ i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,\n+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE,\n+ base_hartid, hart_count,\n+ RISCV_ACLINT_DEFAULT_MTIMECMP,\n+ RISCV_ACLINT_DEFAULT_MTIME,\n+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);\n+\n+ /* Per-socket interrupt controller */\n+ s->irqchip[i] = rvserver_ref_create_aia(s->aia_guests,\n+ memmap, i, base_hartid,\n+ hart_count);\n+\n+ /* Try to use different IRQCHIP instance based device type */\n+ if (i == 0) {\n+ mmio_irqchip = s->irqchip[i];\n+ pcie_irqchip = s->irqchip[i];\n+ }\n+ if (i == 1) {\n+ pcie_irqchip = s->irqchip[i];\n+ }\n+ }\n+\n+ s->memmap = rvserver_ref_memmap;\n+\n+ /* register system main memory (actual RAM) */\n+ memory_region_add_subregion(system_memory, memmap[RVSERVER_DRAM].base,\n+ machine->ram);\n+\n+ /* boot rom */\n+ memory_region_init_rom(mask_rom, NULL, \"riscv_rvserver_ref_board.mrom\",\n+ memmap[RVSERVER_MROM].size, &error_fatal);\n+ memory_region_add_subregion(system_memory, memmap[RVSERVER_MROM].base,\n+ mask_rom);\n+\n+ memory_region_init_io(reset_syscon_io, NULL, &rvserver_reset_syscon_ops,\n+ NULL, \"reset_syscon_io\",\n+ memmap[RVSERVER_RESET_SYSCON].size);\n+ memory_region_add_subregion(system_memory,\n+ memmap[RVSERVER_RESET_SYSCON].base,\n+ reset_syscon_io);\n+\n+ gpex_pcie_init(system_memory, pcie_irqchip, s);\n+\n+ serial_mm_init(system_memory, memmap[RVSERVER_UART0].base,\n+ 0, qdev_get_gpio_in(mmio_irqchip, RVSERVER_UART0_IRQ), 399193,\n+ serial_hd(0), DEVICE_LITTLE_ENDIAN);\n+\n+ sysbus_create_simple(\"goldfish_rtc\", memmap[RVSERVER_RTC].base,\n+ qdev_get_gpio_in(mmio_irqchip, RVSERVER_RTC_IRQ));\n+\n+ for (i = 0; i < ARRAY_SIZE(s->flash); i++) {\n+ /* Map legacy -drive if=pflash to machine properties */\n+ pflash_cfi01_legacy_drive(s->flash[i],\n+ drive_get(IF_PFLASH, 0, i));\n+ }\n+ rvserver_flash_maps(s, system_memory);\n+\n+ /* load/create device tree */\n+ if (machine->dtb) {\n+ machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);\n+ if (!machine->fdt) {\n+ error_report(\"load_device_tree() failed\");\n+ exit(1);\n+ }\n+ } else {\n+ create_fdt(s, memmap);\n+ }\n+\n+ iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);\n+ object_property_set_uint(OBJECT(iommu_sys), \"addr\",\n+ s->memmap[RVSERVER_IOMMU_SYS].base,\n+ &error_fatal);\n+\n+ object_property_set_uint(OBJECT(iommu_sys), \"base-irq\",\n+ IOMMU_SYS_IRQ,\n+ &error_fatal);\n+\n+ object_property_set_link(OBJECT(iommu_sys), \"irqchip\",\n+ OBJECT(mmio_irqchip),\n+ &error_fatal);\n+\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);\n+\n+ s->machine_done.notify = rvserver_ref_machine_done;\n+ qemu_add_machine_init_done_notifier(&s->machine_done);\n+}\n+\n+static void rvserver_ref_machine_instance_init(Object *obj)\n+{\n+ RISCVServerRefMachineState *s = RISCV_SERVER_REF_MACHINE(obj);\n+\n+ s->flash[0] = rvserver_flash_create(s, \"riscv-server-ref.flash0\",\n+ \"pflash0\");\n+ s->flash[1] = rvserver_flash_create(s, \"riscv-server-ref.flash1\",\n+ \"pflash1\");\n+}\n+\n+static char *rvserver_ref_get_aia_guests(Object *obj, Error **errp)\n+{\n+ RISCVServerRefMachineState *s = RISCV_SERVER_REF_MACHINE(obj);\n+ char val[32];\n+\n+ sprintf(val, \"%d\", s->aia_guests);\n+ return g_strdup(val);\n+}\n+\n+static void rvserver_ref_set_aia_guests(Object *obj, const char *val,\n+ Error **errp)\n+{\n+ RISCVServerRefMachineState *s = RISCV_SERVER_REF_MACHINE(obj);\n+\n+ s->aia_guests = atoi(val);\n+ if (s->aia_guests < 0 || s->aia_guests > RVSERVER_IRQCHIP_MAX_GUESTS) {\n+ error_setg(errp, \"Invalid number of AIA IMSIC guests\");\n+ error_append_hint(errp, \"Valid values be between 0 and %d.\\n\",\n+ RVSERVER_IRQCHIP_MAX_GUESTS);\n+ }\n+}\n+\n+static void rvserver_ref_machine_class_init(ObjectClass *oc, const void *data)\n+{\n+ char str[128];\n+ MachineClass *mc = MACHINE_CLASS(oc);\n+ static const char * const valid_cpu_types[] = {\n+ TYPE_RISCV_CPU_RVSERVER_REF,\n+ };\n+\n+ mc->desc = \"RISC-V Server SoC Reference board\";\n+ mc->init = rvserver_ref_machine_init;\n+ mc->max_cpus = RVSERVER_CPUS_MAX;\n+ mc->default_cpu_type = TYPE_RISCV_CPU_RVSERVER_REF;\n+ mc->valid_cpu_types = valid_cpu_types;\n+ mc->pci_allow_0_address = true;\n+ mc->default_nic = \"e1000e\";\n+ mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;\n+ mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;\n+ mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;\n+ mc->numa_mem_supported = true;\n+ /* platform instead of architectural choice */\n+ mc->cpu_cluster_has_numa_boundary = true;\n+ mc->default_ram_id = \"riscv_rvserver_ref_board.ram\";\n+\n+ object_class_property_add_str(oc, \"aia-guests\",\n+ rvserver_ref_get_aia_guests,\n+ rvserver_ref_set_aia_guests);\n+ sprintf(str, \"Set number of guest MMIO pages for AIA IMSIC. Valid value \"\n+ \"should be between 0 and %d.\", RVSERVER_IRQCHIP_MAX_GUESTS);\n+ object_class_property_set_description(oc, \"aia-guests\", str);\n+}\n+\n+static const TypeInfo rvserver_ref_typeinfo = {\n+ .name = TYPE_RISCV_SERVER_REF_MACHINE,\n+ .parent = TYPE_MACHINE,\n+ .class_init = rvserver_ref_machine_class_init,\n+ .instance_init = rvserver_ref_machine_instance_init,\n+ .instance_size = sizeof(RISCVServerRefMachineState),\n+};\n+\n+static void rvserver_ref_init_register_types(void)\n+{\n+ type_register_static(&rvserver_ref_typeinfo);\n+}\n+\n+type_init(rvserver_ref_init_register_types)\n", "prefixes": [ "v5", "3/4" ] }