Patch Detail
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GET /api/1.1/patches/2227848/?format=api
{ "id": 2227848, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227848/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424111330.702272-10-changhuang.liang@starfivetech.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260424111330.702272-10-changhuang.liang@starfivetech.com>", "date": "2026-04-24T11:13:19", "name": "[v1,09/20] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ced57defae29d91717446ad70df17da7f114a3ed", "submitter": { "id": 85771, "url": "http://patchwork.ozlabs.org/api/1.1/people/85771/?format=api", "name": "Changhuang Liang", "email": "changhuang.liang@starfivetech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424111330.702272-10-changhuang.liang@starfivetech.com/mbox/", "series": [ { "id": 501347, "url": "http://patchwork.ozlabs.org/api/1.1/series/501347/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501347", "date": "2026-04-24T11:13:16", "name": "Add basic pinctrl drivers for JHB100 SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501347/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227848/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227848/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35481-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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<kernel@esmil.dk>,\n\tPaul Walmsley <pjw@kernel.org>,\n\tAlbert Ou <aou@eecs.berkeley.edu>,\n\tPalmer Dabbelt <palmer@dabbelt.com>,\n\tAlexandre Ghiti <alex@ghiti.fr>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>,\n\tBartosz Golaszewski <brgl@kernel.org>", "Cc": "linux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-riscv@lists.infradead.org,\n\tLianfeng Ouyang <lianfeng.ouyang@starfivetech.com>,\n\tChanghuang Liang <changhuang.liang@starfivetech.com>", "Subject": "[PATCH v1 09/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per0-pinctrl", "Date": "Fri, 24 Apr 2026 04:13:19 -0700", "Message-Id": "<20260424111330.702272-10-changhuang.liang@starfivetech.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260424111330.702272-1-changhuang.liang@starfivetech.com>", "References": "<20260424111330.702272-1-changhuang.liang@starfivetech.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": 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"X-OriginatorOrg": "starfivetech.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 28a34350-c842-4c35-241c-08dea1f2900f", "X-MS-Exchange-CrossTenant-AuthSource": "\n ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Apr 2026 11:13:50.5237\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "06fe3fa3-1221-43d3-861b-5a4ee687a85c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n x8+qTJ2ZwI6h7dK6wY8RwzE7Dmm9rSKiS4o3yvxp49ntO+SGMQddNa/e76o+l4BLADLeeuB7Z/U35oahP1LM6KKXfVhcxFr6Mz/W/Y6PAEb45/zwC2KoDdmsrdpsHblY", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "ZQ4PR01MB1156" }, "content": "Add pinctrl bindings for StarFive JHB100 SoC Peripheral-0(per0) pinctrl\ncontroller.\n\nSigned-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>\n---\n .../pinctrl/starfive,jhb100-per0-pinctrl.yaml | 219 ++++++++++++++++++\n 1 file changed, 219 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml\nnew file mode 100644\nindex 000000000000..b69b9b21cac6\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml\n@@ -0,0 +1,219 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per0-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: StarFive JHB100 Peripheral-0 Pin Controller\n+\n+description: |\n+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.\n+\n+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,\n+ per2, per2pok, per3, adc0, adc1, emmc, and vga.\n+ This document provides an overview of the \"per0\" pinctrl domain.\n+\n+ The \"per0\" domain has a pin controller which provides\n+ - function selection for GPIO pads.\n+ - GPIO pad configuration.\n+ - GPIO interrupt handling.\n+\n+ In the Peripheral-0 Pin Controller, there are 60 multi-function GPIO_PADs. Each of them\n+ can be multiplexed to several hardware blocks through function selection. Each iopad\n+ has a maximum of up to 3 functions - 0, 1, and 2. Function 0 is the default function\n+ which is generally the GPIO function. Function 1 and 2 are the alternate function or\n+ signal of an iopad. The function 1 and function 2 are other optional functions or\n+ peripheral signals that can be routed to an iopad. The function selection can be carried\n+ out by writing the function number to the iopad function select register.\n+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down\n+ bias, push-pull/Open-drain mode select, schmitt trigger, open-drain pull-up select,\n+ and debounce width.\n+\n+ This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V\n+ gpioe-i3c0 - comprises PAD_GPIO_B8 through PAD_GPIO_B11, PAD_GPIO_B32, and PAD_GPIO_B33.\n+ gpioe-i3c1 - comprises PAD_GPIO_B12 through PAD_GPIO_B15, PAD_GPIO_B34, and PAD_GPIO_B35.\n+ gpioe-i3c2 - comprises PAD_GPIO_B16 through PAD_GPIO_B23.\n+ gpioe-i3c4 - comprises PAD_GPIO_B36 through PAD_GPIO_B43.\n+\n+ Each of the above IO groups must be configured with a voltage setting that matches the external\n+ voltage level provided to the IO group.\n+\n+maintainers:\n+ - Alex Soo <yuklin.soo@starfivetech.com>\n+\n+properties:\n+ compatible:\n+ items:\n+ - const: starfive,jhb100-per0-pinctrl\n+\n+ reg:\n+ maxItems: 1\n+\n+ clocks:\n+ maxItems: 1\n+\n+ resets:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ interrupt-controller: true\n+\n+ '#interrupt-cells':\n+ const: 2\n+\n+ gpio-controller: true\n+\n+ '#gpio-cells':\n+ const: 2\n+\n+ gpio-ranges:\n+ maxItems: 1\n+\n+ gpio-line-names: true\n+\n+ gpioe-i3c0-vref:\n+ description: |\n+ Voltage reference value for the IO group \"gpioe-i3c0\"\n+ 0: voltage reference value for 3.3V\n+ 2: voltage reference value for 1.8V\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [0, 2]\n+ default: 0\n+\n+ gpioe-i3c1-vref:\n+ description: |\n+ Voltage reference value for the IO group \"gpioe-i3c1\"\n+ 0: voltage reference value for 3.3V\n+ 2: voltage reference value for 1.8V\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [0, 2]\n+ default: 0\n+\n+ gpioe-i3c2-vref:\n+ description: |\n+ Voltage reference value for the IO group \"gpioe-i3c2\"\n+ 0: voltage reference value for 3.3V\n+ 2: voltage reference value for 1.8V\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [0, 2]\n+ default: 0\n+\n+ gpioe-i3c4-vref:\n+ description: |\n+ Voltage reference value for the IO group \"gpioe-i3c4\"\n+ 0: voltage reference value for 3.3V\n+ 2: voltage reference value for 1.8V\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [0, 2]\n+ default: 0\n+\n+patternProperties:\n+ '-grp$':\n+ type: object\n+ additionalProperties: false\n+ patternProperties:\n+ '-pins$':\n+ type: object\n+ description: |\n+ A pinctrl node should contain at least one subnode representing the\n+ pinctrl groups available in the domain. Each subnode will list the\n+ pins it needs, and how they should be configured, with regard to\n+ function selection, bias, input enable/disable, input schmitt\n+ trigger enable/disable, slew-rate and drive strength.\n+ allOf:\n+ - $ref: /schemas/pinctrl/pincfg-node.yaml\n+ - $ref: /schemas/pinctrl/pinmux-node.yaml\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pinmux:\n+ description: |\n+ The list of GPIOs and their function select.\n+ The PINMUX macros are used to configure the\n+ function selection.\n+\n+ bias-disable: true\n+\n+ bias-pull-up:\n+ type: boolean\n+\n+ bias-pull-down:\n+ type: boolean\n+\n+ drive-strength:\n+ enum: [ 2, 4, 8, 12 ]\n+\n+ drive-strength-microamp:\n+ enum: [ 2000, 4000, 8000, 12000 ]\n+\n+ input-enable: true\n+\n+ input-disable: true\n+\n+ input-schmitt-enable: true\n+\n+ input-schmitt-disable: true\n+\n+ slew-rate:\n+ enum: [ 0, 1 ]\n+ default: 0\n+ description: |\n+ 0: slow (half frequency)\n+ 1: fast\n+\n+ starfive,debounce-width:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ default: 0\n+ description:\n+ Debounce width 0 = Disabled, Others = 80ns*N stages\n+\n+ starfive,drive-i2c-fast-mode:\n+ type: boolean\n+ description:\n+ Enable I2C fast mode drive\n+\n+ starfive,drive-i2c-fast-mode-plus:\n+ type: boolean\n+ description:\n+ Enable I2C fast mode plus drive\n+\n+ starfive,i2c-open-drain-pull-up-ohm:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ open drain pull-up select\n+ enum: [600, 900, 1200, 2000]\n+ default: 600\n+\n+required:\n+ - compatible\n+ - reg\n+ - resets\n+ - interrupts\n+ - interrupt-controller\n+ - '#interrupt-cells'\n+ - gpio-controller\n+ - '#gpio-cells'\n+ - gpio-ranges\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pinctrl_per0: pinctrl@11a0a000 {\n+ compatible = \"starfive,jhb100-per0-pinctrl\";\n+ reg = <0x0 0x11a0a000 0x0 0x1000>;\n+ resets = <&per0crg 0>;\n+ interrupts = <60>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&pinctrl_per0 0 0 60>;\n+ };\n+ };\n", "prefixes": [ "v1", "09/20" ] }