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GET /api/1.1/patches/2227822/?format=api
{ "id": 2227822, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227822/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424102800.24022-3-frank.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260424102800.24022-3-frank.chang@sifive.com>", "date": "2026-04-24T10:27:58", "name": "[2/4] target/riscv: Support raising misaligned exceptions for scalar loads/stores", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "194e9c0947a0fd114af6fbfe8fd8e118629954f0", "submitter": { "id": 79604, "url": "http://patchwork.ozlabs.org/api/1.1/people/79604/?format=api", "name": "Frank Chang", "email": "frank.chang@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424102800.24022-3-frank.chang@sifive.com/mbox/", "series": [ { "id": 501338, "url": "http://patchwork.ozlabs.org/api/1.1/series/501338/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501338", "date": "2026-04-24T10:27:56", "name": "Support the true Zicclsm extension", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501338/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227822/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227822/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=IRPiZdws;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x632.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nWhen the Zicclsm extension is not enabled, raise misaligned load/store\nexceptions for misaligned accesses from scalar load/store instructions.\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/insn_trans/trans_rvi.c.inc | 6 ++++++\n 1 file changed, 6 insertions(+)", "diff": "diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc\nindex 2c82ae41a77..2662fc5c2a2 100644\n--- a/target/riscv/insn_trans/trans_rvi.c.inc\n+++ b/target/riscv/insn_trans/trans_rvi.c.inc\n@@ -413,6 +413,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)\n if (ctx->cfg_ptr->ext_zama16b) {\n memop |= MO_ATOM_WITHIN16;\n }\n+ if (!ctx->cfg_ptr->ext_zicclsm) {\n+ memop |= MO_ALIGN;\n+ }\n decode_save_opc(ctx, 0);\n if (get_xl(ctx) == MXL_RV128) {\n out = gen_load_i128(ctx, a, memop);\n@@ -524,6 +527,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)\n if (ctx->cfg_ptr->ext_zama16b) {\n memop |= MO_ATOM_WITHIN16;\n }\n+ if (!ctx->cfg_ptr->ext_zicclsm) {\n+ memop |= MO_ALIGN;\n+ }\n decode_save_opc(ctx, 0);\n if (get_xl(ctx) == MXL_RV128) {\n return gen_store_i128(ctx, a, memop);\n", "prefixes": [ "2/4" ] }