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GET /api/1.1/patches/2227775/?format=api
{ "id": 2227775, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227775/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424083837.214947-3-adityag@linux.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260424083837.214947-3-adityag@linux.ibm.com>", "date": "2026-04-24T08:38:29", "name": "[v6,02/10] ppc/mpipl: Implement S0 SBE interrupt", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f686ca25ddc72260dd27158f8f5b344f64860210", "submitter": { "id": 86610, "url": "http://patchwork.ozlabs.org/api/1.1/people/86610/?format=api", "name": "Aditya Gupta", "email": "adityag@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424083837.214947-3-adityag@linux.ibm.com/mbox/", "series": [ { "id": 501318, "url": "http://patchwork.ozlabs.org/api/1.1/series/501318/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501318", "date": "2026-04-24T08:38:28", "name": "Implement MPIPL for PowerNV", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/501318/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227775/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227775/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 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:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=pp1; bh=h6e0Ld9GyXjt/9CgK\n FlSYjhYhBYMTPq6Wjq4dgR2vkU=; b=HpGEp3ZjBD7m+gER88jFgO1erQuq6JCUy\n 5lGONbyzDa3CKn8yEWA8L9kz8GKdam+NpNXYhoyDWXnm3f6PatCpp0UgxLX2uYqa\n Vt+RnLh/0jfWvhcLpL9UfLa8q4gr0r8R56CtoFtYFgq7puo611bMtyLXbCveV+Za\n qwC0Lj1BdFKTMe3mpiJylYB7V8ltL0dqZ80p8I89bcwRkqzGVxp8gpWUdZIkJP4x\n J8XNSVTlZtpcvJqZxqZM7y/lbyxeXwwci0kFTPacOoAYeP4NYqYIaMFhq47lj1io\n aDSiPkZfrmA1jWJIJOPeeGfWjVruotXAHRq6612hNz4LbaXtYMSzw==", "From": "Aditya Gupta <adityag@linux.ibm.com>", "To": "<qemu-devel@nongnu.org>", "Cc": "<qemu-ppc@nongnu.org>, Hari Bathini <hbathini@linux.ibm.com>,\n Sourabh Jain <sourabhjain@linux.ibm.com>,\n Harsh Prateek Bora <harshpb@linux.ibm.com>,\n Nicholas Piggin <npiggin@gmail.com>,\n Miles Glenn <milesg@linux.ibm.com>, Chinmay Rath <rathc@linux.ibm.com>,\n Shivang Upadhyay <shivangu@linux.ibm.com>", "Subject": "[PATCH v6 02/10] ppc/mpipl: Implement S0 SBE interrupt", "Date": "Fri, 24 Apr 2026 14:08:29 +0530", "Message-ID": "<20260424083837.214947-3-adityag@linux.ibm.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260424083837.214947-1-adityag@linux.ibm.com>", "References": "<20260424083837.214947-1-adityag@linux.ibm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-Reinject": "loops=2 maxloops=12", "X-Proofpoint-ORIG-GUID": "AOsbdYGPYn7gWzUY9JjN92aaT0GcRcTV", "X-Authority-Analysis": "v=2.4 cv=Ksp9H2WN c=1 sm=1 tr=0 ts=69eb2c2c cx=c_pps\n a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22\n a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=atcXKtye3xvqEmVJAE4A:9", "X-Proofpoint-GUID": "PySs8pHEaPGGVTztPrTdv00pOr9KTVGA", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI0MDA3NiBTYWx0ZWRfXzbuV46nNFqnj\n z5NIR9Sta3OOSyv4G/E3HIyKRrS2H/ywh8TO6kqEng9LFgaXT164xAAF/vM/GUNIpUhajhFxHxj\n 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client-ip=148.163.158.5;\n envelope-from=adityag@linux.ibm.com;\n helo=mx0b-001b2d01.pphosted.com", "X-Spam_score_int": "-26", "X-Spam_score": "-2.7", "X-Spam_bar": "--", "X-Spam_report": "(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "During MPIPL (aka fadump), after a kernel crash, the kernel does\nopal_cec_reboot2 opal call, signifying an abnormal termination.\nWhen OPAL receives this opal call, it further triggers SBE S0 interrupt,\nto trigger a MPIPL boot.\n\nCurrently S0 interrupt is unimplemented in QEMU.\n\nImplement S0 interrupt as 'pause_vcpus' + 'guest_reset' in QEMU, as the\nSBE's implementation of S0 seems to be basically \"stop all clocks\" and\nthen \"host reset\".\n\npause_vcpus is done in a later patch when register preserving support is\nadded\n\nSee 'stopClocksS0' in SBE source code for more information.\n\nAlso log both S0 and S1 interrupts.\n\nReviewed-by: Hari Bathini <hbathini@linux.ibm.com>\nReviewed-by: Sourabh Jain <sourabhjain@linux.ibm.com>\nSigned-off-by: Aditya Gupta <adityag@linux.ibm.com>\n---\n hw/ppc/meson.build | 1 +\n hw/ppc/pnv_mpipl.c | 26 ++++++++++++++++++++++++++\n hw/ppc/pnv_sbe.c | 29 +++++++++++++++++++++++++++++\n include/hw/ppc/pnv.h | 5 +++++\n include/hw/ppc/pnv_mpipl.h | 19 +++++++++++++++++++\n 5 files changed, 80 insertions(+)\n create mode 100644 hw/ppc/pnv_mpipl.c\n create mode 100644 include/hw/ppc/pnv_mpipl.h", "diff": "diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build\nindex f7dac87a2a48..c61fba4ec8f2 100644\n--- a/hw/ppc/meson.build\n+++ b/hw/ppc/meson.build\n@@ -56,6 +56,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(\n 'pnv_pnor.c',\n 'pnv_nest_pervasive.c',\n 'pnv_n1_chiplet.c',\n+ 'pnv_mpipl.c',\n ))\n # PowerPC 4xx boards\n ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(\ndiff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c\nnew file mode 100644\nindex 000000000000..d8c9b7a428b7\n--- /dev/null\n+++ b/hw/ppc/pnv_mpipl.c\n@@ -0,0 +1,26 @@\n+/*\n+ * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"system/runstate.h\"\n+#include \"hw/ppc/pnv.h\"\n+#include \"hw/ppc/pnv_mpipl.h\"\n+\n+void do_mpipl_preserve(PnvMachineState *pnv)\n+{\n+ /* Mark next boot as Memory-preserving boot */\n+ pnv->mpipl_state.is_next_boot_mpipl = true;\n+\n+ /*\n+ * Do a guest reset.\n+ * Next reset will see 'is_next_boot_mpipl' as true, and trigger MPIPL\n+ *\n+ * Requirement:\n+ * GUEST_RESET is expected to NOT clear the memory, as is the case when\n+ * this is merged\n+ */\n+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n+}\ndiff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c\nindex 247617338a0d..5a2b3342d199 100644\n--- a/hw/ppc/pnv_sbe.c\n+++ b/hw/ppc/pnv_sbe.c\n@@ -26,6 +26,9 @@\n #include \"hw/ppc/pnv.h\"\n #include \"hw/ppc/pnv_xscom.h\"\n #include \"hw/ppc/pnv_sbe.h\"\n+#include \"hw/ppc/pnv_mpipl.h\"\n+#include \"system/cpus.h\"\n+#include \"system/runstate.h\"\n #include \"trace.h\"\n \n /*\n@@ -113,11 +116,37 @@ static uint64_t pnv_sbe_power9_xscom_ctrl_read(void *opaque, hwaddr addr,\n static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr,\n uint64_t val, unsigned size)\n {\n+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());\n+ PnvSBE *sbe = opaque;\n uint32_t offset = addr >> 3;\n \n trace_pnv_sbe_xscom_ctrl_write(addr, val);\n \n switch (offset) {\n+ case SBE_CONTROL_REG_RW:\n+ switch (val) {\n+ case SBE_CONTROL_REG_S0:\n+ qemu_log_mask(LOG_UNIMP, \"SBE: S0 Interrupt triggered\\n\");\n+\n+ pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_RESPONSE_MASK);\n+\n+ /* Preserve memory regions and CPU state, if MPIPL is registered */\n+ do_mpipl_preserve(pnv);\n+\n+ /*\n+ * Control may not come back here as 'do_mpipl_preserve' triggers\n+ * a guest reboot\n+ */\n+ break;\n+ case SBE_CONTROL_REG_S1:\n+ qemu_log_mask(LOG_UNIMP, \"SBE: S1 Interrupt triggered\\n\");\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP,\n+ \"SBE: CONTROL_REG_RW: Unknown value: Ox%.\"\n+ HWADDR_PRIx \"\\n\", val);\n+ }\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"SBE Unimplemented register: Ox%\"\n HWADDR_PRIx \"\\n\", addr >> 3);\ndiff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h\nindex 90028f974dab..79de6b856923 100644\n--- a/include/hw/ppc/pnv.h\n+++ b/include/hw/ppc/pnv.h\n@@ -25,6 +25,7 @@\n #include \"hw/core/sysbus.h\"\n #include \"hw/ipmi/ipmi.h\"\n #include \"hw/ppc/pnv_pnor.h\"\n+#include \"hw/ppc/pnv_mpipl.h\"\n \n #define TYPE_PNV_CHIP \"pnv-chip\"\n \n@@ -113,6 +114,7 @@ struct PnvMachineState {\n bool lpar_per_core;\n \n Notifier machine_init_done;\n+ MpiplPreservedState mpipl_state;\n };\n \n PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);\n@@ -292,4 +294,7 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);\n \n #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)\n \n+/* MPIPL helpers */\n+void do_mpipl_preserve(PnvMachineState *pnv);\n+\n #endif /* PPC_PNV_H */\ndiff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h\nnew file mode 100644\nindex 000000000000..61ef7ef8fe60\n--- /dev/null\n+++ b/include/hw/ppc/pnv_mpipl.h\n@@ -0,0 +1,19 @@\n+/*\n+ * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef PNV_MPIPL_H\n+#define PNV_MPIPL_H\n+\n+#include <stdbool.h>\n+\n+typedef struct MpiplPreservedState MpiplPreservedState;\n+\n+/* Preserved state to be saved in PnvMachineState */\n+struct MpiplPreservedState {\n+ bool is_next_boot_mpipl;\n+};\n+\n+#endif\n", "prefixes": [ "v6", "02/10" ] }